Cell death induced by agents that disrupt microtubules can kill cells by inducing a prolonged mitotic block. This mitotic block is dependent on the spindle assembly checkpoint, a surveillance system that ensures the bipolar attachment of chromosomes to the mitotic spindle before the onset of anaphase. Under some conditions, the spindle assembly checkpoint can become weakened, allowing cells to exit mitosis despite the presence of chromosomes that are not properly attached to the mitotic spindle. Here, we use an Aurora kinase inhibitor to drive mitotic exit and test the effect of mitotic arrest length on death in the subsequent interphase. Cells that are blocked in mitosis for >15 h die shortly after exiting from mitosis, whereas cells that exit after being blocked for <15 h show variable fates, with some living for days after exiting mitosis. Cells blocked in mitosis by either Taxol or epothilone B are acutely sensitive to the death ligand tumor necrosis factor-related apoptosisinducing ligand, suggesting that prolonged mitosis allows the gradual accumulation of internal death signals, rendering cells hypersensitive to additional prodeath cues. Death under these conditions is initiated while cyclin B1 is still present, indicating that cells are in mitosis. Our experiments suggest that there is a point of no return during prolonged mitotic block after which mitotic exit can no longer block death.

New technologies such as 3D integration are becoming a new force that is keeping Moore's law in effect in today's nano era. By adding a third dimension in current 2D circuits, we can greatly increase integration density, reduce interconnection length, and enable heterogeneous systems within one package. In order to exploit the advantages of 3D integration, layout designers and tool developers need to be fully aware of this rapid development. This paper gives an overview of recent 3D integration technologies, such as 3D packages and 3D integrated circuits. We then analyze and compare 3D data structures in order to draw conclusions about their future potential. Finally, the impact of 3D technologies on interconnect prediction is discussed.

During the design of 2.5D and 3D integrated systems the thermal management of the whole system is important, especially in high performance systems with combinations of processor and memory dies utilizing the Wide I/O memory interface. Because cooling solutions could be very expensive they should be considered in very early design cycles. For example, the decision if the system is implemented as a real stacked system or using an interposer strongly influences the required cooling solution. Furthermore, high performance systems with data transfer rates in the range of 100 Gbit/s to 400 Gbit/s between processo r and memory req uire an early and fast floorplan calculation to determine and optimize the heat distribution within the system (i.e., dies and package).In this paper, an appropriate floorplanner with direct access to an octree based finite element solver for the calculation of the heat distribution of the whole system is presented. Our approach allows an efficient design space exploration. The thermal simulation on system level, including heatsink and package, makes it unnecessary to manually set the boundary conditions of the chips. Thus, this approach prevents possible errors caused by this step.To illustrate the new analysis and optimization approach, it is applied to a Wide I/O 2.5D or 3D integrated system, respectively.

The current trend towards 3D integration requires new layout representations specifically designed to take 3D-specific constraints into account and to facilitate efficient design algorithms. We observe that it is difficult to compare and evaluate these layout-specific data structures. In this paper, we first present a detailed investigation of modern layout representations while analyzing their solution space and their characteristics, such as redundancy and reachability. Our investigation reveals their potential for 3D applications but also shows open challenges to be considered for (future) representations. Thus, we also provide guidelines for designing efficient layout representations. Finally, we release our investigation methodology as open-source tool, thus providing interested researchers with the opportunity to conduct reasonable evaluations on their own.

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