From 3D circuit technologies and data structures to interconnect prediction

Fischbach, Robert; Lienig, Jens; Meister, Tilo

doi:10.1145/1572471.1572485

Cited by 25 publications

(11 citation statements)

References 21 publications

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“…Finalverhead in function of the FIFO take into account the area of the y, throughput and power conthe others in the literature is nitially were not taken into acnumbers shown in Figure 9 and by roughly a factor of 1.4 [27], y, power consumption, and area cy, Throughput and Power Con-64. [28], [29] to make them comparable with designs in [24], [26]. Nevertheless the latency, throughput and power of our design are better than the others.…”

Section: Resultsmentioning

confidence: 91%

A high-throughput, metastability-free GALS channel based on pausible clock method

Rahimian

Mohammadi

Fattah

2010

2nd Asia Symposium on Quality Electronic Design (ASQED)

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Synchronization issues such as metastability in multi-clock domain systems have become a big problem, reducing data transmission throughput between domains. In this paper, a high-throughput, metastability-free data transmission channel based on pausible clock method in Globally-Asynchronous Locally-Synchronous (GALS) systems is proposed. This channel can be used as the interconnection of mixed-clock synchronous IP cores without having concerns about their synchronization. We show that the probability of metastability in our design is practically zero; and this without loss of throughput and latency, allowing the transmitter and receiver to operate with their own maximum clock frequency. The proposed channel is simulated in 90nm CMOS process using Predictive Technology Model (PTM) library. Gate delays and power parameters are extracted from Spice simulations and are back annotated into our channel HDL code. The throughput, latency and power are analyzed and compared with existing designs.

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Section: Resultsmentioning

confidence: 91%

A high-throughput, metastability-free GALS channel based on pausible clock method

Rahimian

Mohammadi

Fattah

2010

2nd Asia Symposium on Quality Electronic Design (ASQED)

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“…Further, interposer allow for better heat dissipation [17], [50]. In short, interposer are considered as the platform for "new multi-chip modules (MCMs)" [51], [52], with low cost, high yield, and the combination of heterogeneous integrated circuits in one package cited as the major advantages.…”

Section: Interposer Stacksmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…Finer granularity of 3D integration is enabled by connecting dies with TSVs, which results in 3D ICs [5]. In this section, we first discuss gate-level and block-level integration styles for 3D ICs.…”

Section: D Ic Design Stylesmentioning

confidence: 99%

“…5 The GSRC and MCNC benchmarks included in this infrastructure do not provide pin offsets, therefore we assume net bounding boxes to be defined by the bounding boxes of incident blocks. Two sets of floorplans are obtained, configuring the floorplanner for 10% and 15% deadspace respectively.…”

Section: Empirical Validationmentioning

confidence: 99%

Assembling 2-D Blocks Into 3-D Chips

Knechtel

Markov

Lienig

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been slow. In addition to technology-related difficulties, industry experts cite the lack of a commercial 3D EDA tool-chain and design standards, high risk associated with a new technology, and high cost of transition from 2D to 3D ICs. To streamline the transition, we explore design styles that reuse existing 2D Intellectual Property (IP) blocks. Currently, these design styles severely limit the placement of Through-Silicon Vias (TSVs) and constrain the reuse of existing 2D IP blocks in 3D ICs. To overcome this problem, we develop a methodology for using TSV islands and novel techniques for clustering nets to connect 2D IP blocks through TSV islands. Our empirical validation demonstrates 3D integration of traditional 2D circuit blocks without modifying their layout for this context.

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From 3D circuit technologies and data structures to interconnect prediction

Cited by 25 publications

References 21 publications

A high-throughput, metastability-free GALS channel based on pausible clock method

A high-throughput, metastability-free GALS channel based on pausible clock method

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Assembling 2-D Blocks Into 3-D Chips

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