Investigating modern layout representations for improved 3d design automation

Fischbach, Robert; Lienig, Jens; Knechtel, Johann

doi:10.1145/1973009.1973076

Cited by 9 publications

(5 citation statements)

References 16 publications

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“…The above requirements are notably harder to achieve for the 3D solution space than it has been in the case for "classical" 2D design automation [69], [70]. Still, efficient data structures initially developed for the physical design of 2D ICs (notably the Slicing Tree, the O-Tree or the Sequence Pair) have been successfully extended towards 3D integration.…”

Section: Data Structures and Solution Spacementioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Data Structures and Solution Spacementioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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“…2 Existing floorplanning methodologies already address key challenges such as thermal management [27,[34][35][36], co-arrangement of modules and TSVs [59] or planning of system-level buses [27,36,60]. Still, 3D floorplanning is a highly technology-dependent and iterative process-fast, accurate and configurable design evaluation is currently targeted but still to be enhanced [61,62]. So far, only few tools offer high-level, multi-objective exploration, which is needed for microarchitecture-focused 3D design [55,63].…”

Section: Partitioning and Floorplanningmentioning

confidence: 99%

Physical Design Automation for 3D Chip Stacks

Knechtel¹,

Lienig²

2016

Proceedings of the 2016 on International Symposium on Physical Design

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The concept of 3D chip stacks has been advocated by both industry and academia for many years, and hailed as one of the most promising approaches to meet ever-increasing demands for performance, functionality and power consumption going forward. However, a multitude of challenges has thus far obstructed large-scale transition from "classical" 2D chips to stacked 3D chips. We survey major design challenges for 3D chip stacks with particular focus on their implications for physical design. We also derive requirements for advances in design automation, such as the need for a unified workflow. Finally, we outline current promising solutions as well as areas needing further research and development. bly design kit; design standards 2. 3D-CHIP STACKING OPTIONS AND HIGH-LEVEL DESIGN CHALLENGES 3D-chip stacking falls into four categories (Fig. 2): (i) package stacking, (ii) interposer stacks, (iii) through-silicon via (TSV)based 3D ICs, and (iv) monolithic 3D ICs. Each option has its This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike International 4.0 License.

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“…We perform 100 full optimization runs for each combination of benchmark and representation, providing detailed cost distributions. (Such distributions are helpful for investigations of the solution quality of 3D layout representations; for further reading refer to [33].) Figure 9 illustrates such distributions for the (original) benchmark ami33 as box plots; results for further MCNC benchmarks are provided in Table 3.…”

Section: Floorplanning Of Rectangular Blocksmentioning

confidence: 99%

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems

Fischbach¹,

Knechtel²,

Lienig³

2013

Proceedings of the 2013 ACM International Symposium on Physical Design

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The reuse of predesigned intellectual property (IP) blocks is critical for the commercial success of three-dimensional (3D) electronic circuits. In practice, IP blocks can be specified as rectangular as well as rectilinear 2D blocks. The 3D equivalent of 2D rectilinear blocks, orthogonal polyhedra, may be utilized for modeling tightly interconnected (sub-)modules placed onto adjacent dies or for design automation of versatile 3D-integrated systems. Such complex block geometries have not been adequately considered until now. We propose a new 3D layout representation that enables native 3D floorplanning of complex-shaped 3D blocks, i.e., orthogonal poly-hedra spread onto multiple dies. Furthermore, it can also be applied during 3D floorplanning of both rectangular and rectilinear 2D blocks. In the former case, experiments reveal superior estimated wirelength and packing density compared to previous work

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Investigating modern layout representations for improved 3d design automation

Cited by 9 publications

References 16 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Physical Design Automation for 3D Chip Stacks

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems

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