2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE) 2022
DOI: 10.23919/date54114.2022.9774574
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AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms

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Cited by 12 publications
(4 citation statements)
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“…NN accelerators are typically based on a hardware architecture that comprises a memory hierarchy and an array of interconnected processing engines (PEs) [4], [7], [8], [9], [10], similar to the one depicted in Figure 1. The memory hierarchy usually comprises the system's main memory (offchip), global buffers (on-chip), and the registers within the processing engines.…”
Section: A Hardware Accelerators and Mappingmentioning
confidence: 99%
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“…NN accelerators are typically based on a hardware architecture that comprises a memory hierarchy and an array of interconnected processing engines (PEs) [4], [7], [8], [9], [10], similar to the one depicted in Figure 1. The memory hierarchy usually comprises the system's main memory (offchip), global buffers (on-chip), and the registers within the processing engines.…”
Section: A Hardware Accelerators and Mappingmentioning
confidence: 99%
“…Figure 10 depicts the utilization of approximation levels for each NN layer. It is possible to notice the presence of peaks around levels with an index equal to or smaller than 2 j − 1, j ∈ [0, 1,2,3,4,5,6,7,8], corresponding to the Pareto optimal points of Figure 8. In Figure 10, it is shown how the majority of approximation levels are used in the Pareto front, justifying the choice to maintain power and MRED-dominated configurations as the most efficient levels might not be optimal ones to achieve a high task accuracy.…”
Section: Benchmark With Cifar-10mentioning
confidence: 99%
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