Analog baseband processor for CDMA/FM portable cellular telephones

Nettles, M.; Chang, Menping; McAllister, Graham; Nise, B.E.; Persico, C.; Sahota, K.; Tero, J.

doi:10.1109/isscc.1995.535575

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Architecture Design Of Dfdc1

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Cited by 16 publications

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“…Also, according to tlie IF processor presented by Qualcomin [6], which digitizes tlie 1 and Q baseband signal with two 4-bits A/D converters, we over-design our AD converter to be 5 bits to give an extra SNR margin for the digital I and Q filters. The sampling rate of this AD converter is 4 times the IF frequency that is 19.6608 MHz.…”

Section: Architecture Design Of Dfdcmentioning

confidence: 99%

Low-power multirate IF digital frequency down converter

Jou

Wang

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

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The architecture design of the proposed IF digital frequency down converter (DFDC) is tlie combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on multirate algoritlun.It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. Design application for IS-95 CDMA with IF frequency at 4.9152 h4Hz shows that the DFDC only consumes 0.6mw when operates at 2 V.

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Section: Architecture Design Of Dfdcmentioning

confidence: 99%