Analog behavior refinement in system centric modeling

Zaidi, Yaseen; Grimm, Christoph; Haase, Jan

doi:10.1109/bmas.2009.5338893

Cited by 3 publications

(3 citation statements)

References 10 publications

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“…Also, SystemC-AMS suffers from the difficulty of modeling nonideal and nonlinear systems, and thus is less accurate compared to VHDL-AMS and Verilog-AMS. For this reason, mixed SystemC-AMS, VHDL-AMS, and Verilog-AMS modeling was suggested in [38]. In this work, we adopted Verilog-AMS and metamodeling to construct a compact and layout-accurate VCO behavioral model used for PLL design space exploration.…”

Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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Electronic circuit behavioral models built with hardware description/modeling languages such as Verilog-AMS for system-level simulations are typically functional models. They do not capture the physical design (layout) information of the target design. Thus, their applications are limited to early design feasibility studies and/or pre-layout functional verification. Numerous iterations of post-layout design adjustments are usually required to ensure that design specifications are met with the presence of layout parasitics. In this paper a paradigm shift of the current trend is presented that integrates layout-level information (with full parasitics) in Verilog-AMS through metamodels such that systemlevel simulation of a mixed-signal circuit/system is realistic and as accurate as true parasitic netlist simulation. The simulations performed with these parasitic-aware models can be used to estimate system performance without layout iterations. We call this new form of Verilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 as it is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design space exploration. The PLL simulation employing quadratic metamodels achieves approximately 10× speedup compared to that employing the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power dissipation are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout-accurate but fast simulation and design space exploration. The proposed method also allows much shorter design verification and optimization to meet stringent time-to-market requirements. In the PLL optimization case study, 46 % PLL power reduction was achieved using a differential evolution algorithm and the proposed layout-accurate behavioral model. Compared to the optimization using the layout netlist, the runtime using the behavioral model is reduced by 88.9 %. To the best of the authors' knowledge this is the first approach that brings layout-level accuracy to system-level design exploration and is applied towards mixed-signal design exploration.

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Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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“…Simple nonlinear static behavior can be approximated with TDF by selecting a rational sampling rate. External solvers [30] can be interfaced with SystemC AMS as well as user defined MoCs [31] can be formally binded. Analog TDF models can interact with TLM-based DE models [32].…”

Section: Modeling With Systemc Amsmentioning

confidence: 99%

“…These simulations will be inherently slow and would deal with typical convergence problem. SystemC AMS to Cadence analog cosimulation issues have been highlighted in [30].…”

Section: Interface Computation Lagmentioning

confidence: 99%

On Mixed Abstraction, Languages, and Simulation Approach to Refinement with SystemC AMS

Zaidi¹,

Grimm²,

Haase³

2010

EURASIP Journal on Embedded Systems

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Executable specifications and simulations are cornerstone to system design flows. Complex-mixed-signal embedded systems can be specified with SystemC AMS which supports abstraction and extensible models of computation. The language contains semantics for module connections and synchronization required in analog and digital interaction. Through the synchronization layer, user defined models of computation, solvers and simulators can be unified in the SystemC AMS simulator for achieving low-level abstraction and model refinement. These improvements assist in amplifying model aspects and their contribution to the overall system behavior. This work presents cosimulating refined models with timed data flow paradigm of SystemC AMS. The methodology uses C-based interaction between simulators. An RTL model of data encryption standard is demonstrated as an example. The methodology is flexible and can be applied in early design decision tradeoff, architecture experimentation, and particularly for model refinement and critical behavior analysis.

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A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits

Vallone,

Hasou,

Colizzi

et al. 2024

2024 25th International Symposium on Quality Electronic Design (ISQED)

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Analog behavior refinement in system centric modeling

Cited by 3 publications

References 10 publications

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

On Mixed Abstraction, Languages, and Simulation Approach to Refinement with SystemC AMS

A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits

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