Analog Hardware Implementations of Artificial Neural Networks

Nedjah, Nadia; Silva, Rodrigo Martins da; Mourelle, Luiza de Macedo

doi:10.1142/s0218126611007347

Cited by 6 publications

(2 citation statements)

References 18 publications

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“…In general, the implementation are very fast, dense and low-power when compared to digital ones, but they come along with precision, data storage, robustness and learning problems, as shown in (Holt and Baker, 1991;Nedjah et al, 2011;Choi et. al., 1996).…”

Section: Related Workmentioning

confidence: 99%

Compact yet efficient hardware architecture for multilayer-perceptron neural networks

Silva

Mourelle

Nedjah

2011

Sba Controle & Automação

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RESUMOArquitetura de hardware compacta e eficiente para redes neurais artificiais do tipo múltiplas camadas Em termos computacionais, uma rede neural artificial (RNA) pode ser implementada em software ou em hardware, ou ainda de maneira híbrida, combinando ambos os recursos. O presente trabalho propõe uma arquitetura de hardware para a computação de uma rede neural do tipo perceptron com múl-tiplas camadas (MLP). Soluções em hardware tendem a ser mais eficientes do que soluções em software. O projeto em questão, além de explorar fortemente o paralelismo das redes neurais, permite alterações do número de entradas, número de camadas e de neurônios por camada, de modo que diversas aplicações de RNAs possam ser executadas no hardware proposto. Visando a uma redução de tempo do processamento aritmético, um número real é aproximado por uma fração de inteiros. Dessa forma, as operações aritméticas limitam-se a operações inteiras, executadas por circuitos combinacionais. Uma simples máquina de estados é demandada para controlar somas e produtos de frações. A função de ativação usada neste projeto é a sigmóide. Essa função é aproximada mediante o uso de polinômios, cujas operações são regidas por somas e produtos. Um teorema é introduzido e provado, permitindo a fundamentação da estratégia de cálculo da função de ativação. Dessa forma, reaproveita-se o circuito aritmé-tico da soma ponderada para também computar a sigmóide. Essa re-utilização dos recursos levou a uma redução drás-tica de área total de circuito. Após modelagem e simulação para validação do bom funcionamento, a arquitetura proposta foi sintetizada utilizando recursos reconfiguráveis, do tipo FPGA. Os resultados são promissores. PALAVRAS-CHAVE:Redes neurais artificiais, hardware para redes neurais, sigmóide, paralelismo, FPGA. ABSTRACTThere are several neural network implementations using either software, hardware-based or a hardware/software codesign. This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP). In this paper, we explore the parallelism of neural networks and allow on-thefly changes of the number of inputs, number of layers and number of neurons per layer of the net. This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware. In order to reduce the processing time that is spent in arithmetic computaRevista Controle & Automação/Vol.22 no.6/Novembro e Dezembro 2011 647 tion, a real number is represented using a fraction of integers. In this way, the arithmetics is limited to integer operations, performed by fast combinational circuits. A simple state machine is required to control sums and products of fractions. Sigmoid is used as the activation function in the proposed implementation. It is approximated by polynomials, whose underlying computation requires only sums and products. A theorem is introduced and proven so as to cover the arithmetic strategy of the computation of the activation function. T...

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Section: Related Workmentioning

confidence: 99%

Compact yet efficient hardware architecture for multilayer-perceptron neural networks

Silva

Mourelle

Nedjah

2011

Sba Controle & Automação

Self Cite

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“…These software implementations are generally unsuitable for real-time applications, due to the fact that the algorithms require a large number of iterations to achieve convergence. Moreover, the intrinsic parallelism in the algorithm execution is difficult to achieve in a mono-processor computing system [15]. Therefore, in order to cope efficiently with signal reconstruction problem in compressive sensing, one needs a dedicated parallel hardware implementation of reconstruction algorithm.…”

Section: Introductionmentioning

confidence: 99%

An analog hardware solution for compressive sensing reconstruction using gradient-based method

Orović

Lekić

Beko

et al. 2019

EURASIP J. Adv. Signal Process.

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This work proposes an analog implementation of gradient-based algorithm for compressive sensing signal reconstruction. Compressive sensing has appeared as a promising technique for efficient acquisition and reconstruction of sparse signals in many real-world applications. It starts from the assumption that sparse signals can be exactly reconstructed using far less samples than in standard signal processing. In this paper, we consider the gradient-based algorithm as the optimal choice that provides lower complexity and competitive accuracy compared with existing methods. Since the efficient hardware implementations of reconstruction algorithms are still an emerging topic, this work is focused on the design of hardware that will provide fast parallel algorithm execution for real-time applications, overcoming the limitations imposed by the large number of nested iterations during the signal reconstruction. The proposed implementation is simple and fast, executing 400 iterations in 1 ms which is sufficient to obtain highly accurate reconstruction results.

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Compact yet efficient hardware implementation of artificial neural networks with customized topology

Nedjah

Silva

Mourelle

2012

Expert Systems with Applications

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Analog Hardware Implementations of Artificial Neural Networks

Cited by 6 publications

References 18 publications

Compact yet efficient hardware architecture for multilayer-perceptron neural networks

Compact yet efficient hardware architecture for multilayer-perceptron neural networks

An analog hardware solution for compressive sensing reconstruction using gradient-based method

Compact yet efficient hardware implementation of artificial neural networks with customized topology

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