Compact yet efficient hardware implementation of artificial neural networks with customized topology

Nedjah, Nadia; Silva, Rodrigo Martins da; Mourelle, Luiza de Macedo

doi:10.1016/j.eswa.2012.02.085

Cited by 22 publications

(14 citation statements)

References 19 publications

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“…This has made their use of adders and multipliers adequate but exhibits a great loss of precision. In Nedjah et al, 17 fractions are used to represent real numbers. Comparing the performance results of the proposed representation with ''integer fractions,'' the design has then been compared to three similar implementations.…”

Section: Number Representationmentioning

confidence: 99%

“…19 In this work, we need to design an efficient arithmetic representation that provides good accuracy as well as uses a reduced number of resources. In Nedjah et al, 17 it was shown that the fractional representation model is very interesting. The fractional model is represented by 33 bits in total.…”

Section: Number Representationmentioning

confidence: 99%

“…Methods using multipliers, that is, polynomial methods; 1,17,[25][26][27][28][29][30] Pre-calculated values stored in a look-up table (LUT); 15,31,32 Coordinate rotation digital computer (CORDIC) algorithm. [33][34][35] For instance, the piecewise linear approximation [27][28][29] and the second-order polynomial approximation 17,26,28 of the hyperbolic tangent function were investigated and their fitting parameters were identified by means of the linear least squares algorithm. The complexity of the polynomial expansion can be increased to reach 5 in order to achieve better approximation accuracy.…”

Section: Modeling Of the Activation Functionmentioning

confidence: 99%

“…In the literature, two types of architectures of MLP are used: Serial architecture 15,16 uses a minimum area but requires a lot of time for execution due to the use of a single functional unit. Parallel architecture 15,17,18 allows a very rapid execution through the parallelisms of neurons but uses a very large area.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Faiedh

Hamdi

Bouguezzi

et al. 2018

Proceedings of the Institution of Mechanical Engineers, Part I:

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Road sign recognition is part of the automatic driver assistance systems implemented on the dashboard of vehicles. The recognition task is often carried out based on a classification procedure manipulating the detected signs. Classification tasks can be resolved by the use of multilayer artificial neural network systems. This article proposes an optimized real-time on-chip hardware implementation of multilayer perceptron system used for road sign classification. Four architectural approaches were described: on the one hand, the classic and the serial optimized architectures that offer a very significant reduction in hardware resources, and, on the other hand, the parallel and the optimized architectures, which offer a much reduced, time execution. In order to benefit from the advantages of the allocated hardware resources and the classification of the runtime process, these four architectures have been implemented on field programmable gate array Virtex-6 devices and their performances were quantified and evaluated according to a cost criterion. The energy dissipated by each of these architectures was measured; the achieved results have allowed us to conclude that the serial optimized architecture is the optimal solution, since it creates a tradeoff between the low cost, and the energy efficiency, and still real-time for the considered application.

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Section: Number Representationmentioning

confidence: 99%

Section: Number Representationmentioning

confidence: 99%

Section: Modeling Of the Activation Functionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Faiedh

Hamdi

Bouguezzi

et al. 2018

Proceedings of the Institution of Mechanical Engineers, Part I:

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“…The sequential implementations in most of the cases cannot work in real time, but a parallelized structure of the operations could be a solution. There are many related works to the implementations of neuro-fuzzy models, using different techniques [1], [2], [3]. The best platform to realize embedded systems with parallel architectures is the Field Programmable Gate Array (FPGA).…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of a Neuro-Fuzzy Controller Using High Level Synthesis Tool

Tămas

Brassai

2015

MACRo 2015

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Abstract:The purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.

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Possibility of Hybrid Multilayered Perceptron Neural Network Realisation on FPGA and Its Challenges

Ann

Ehkan

Mashor

2015

Lecture Notes in Electrical Engineering

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Compact yet efficient hardware implementation of artificial neural networks with customized topology

Cited by 22 publications

References 19 publications

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Architectural exploration of multilayer perceptron models for on-chip and real-time road sign classification

Hardware Implementation of a Neuro-Fuzzy Controller Using High Level Synthesis Tool

Possibility of Hybrid Multilayered Perceptron Neural Network Realisation on FPGA and Its Challenges

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