Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

“…The reference consumed approximately 37 μW of total power at T = 25°C. Note that the nominal current mirror drain current was larger than that of the thick‐oxide reference (2.5 μA) because the relative effects of direct tunneling decrease with increasing bias current (see Section 3). However, increases in the nominal drain current beyond 3.3 μA were limited by the minimum voltage headroom needed across the PMOS current mirrors, which was found to be approximately 100 mV.…”

“…As the temperature decreased from 27°C to −40°C, | Δ I G | changed from 2.1 nA to 20.4 nA and Δ V GS changed from −3.1 mV to −20.4 mV. The channel length selection methodology developed in was beneficial in helping minimize | Δ I G | and Δ V GS .…”

“…The transistor-level implementation of the reference was similar to that described in [2] and [3]. Self-cascode structures were used for all current mirrors to increase output resistance [8]. The reference consumed approximately 15 mW of power at T = 25 C. The cascoding (cascoded) devices of the PMOS mirrors were sized with W = 400 mm (160 mm) and L = 0.25 mm (2.5 mm).…”

“…The ultra-thin oxide voltage reference of Figure 5 was designed to determine if the developed techniques could overcome the problems observed in Figure 3. The self-cascode current mirrors were designed to have nominal drain currents of 3.3 mA at T = 25 C. The reference consumed approximately 37 mW of total power at T = 25 C. Note that the nominal current mirror drain current was larger than that of the thick-oxide reference (2.5 mA) because the relative effects of direct tunneling decrease with increasing bias current [8] (see Section 3). However, increases in the nominal drain current beyond 3.3 mA were limited by the minimum voltage headroom needed across the PMOS current mirrors, which was found to be approximately 100 mV.…”

“…In deep sub-micron CMOS technologies (V DD < 1 V), they often produce an output voltage between 500 mV and 800 [2][3][4][5][6][7]. However, none of these so-called sub-1 V bandgap voltage references account for the problems created by direct tunneling-induced gate current, which is prevalent in traditional (non-high-k/metal gate) ultra-thin oxide (t ox < 3 nm) CMOS technologies [8][9][10][11][12].…”