Analog Layout Retargeting

Said, Hazem; Dessouky, Mohamed; El-Adawi, Reem; Abbas, Hazem M.; Shahein, Hussein I.

doi:10.1007/978-1-4419-6932-3_5

Cited by 2 publications

(2 citation statements)

References 28 publications

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“…plexity of layout generation is increasing, which demands new techniques for the generation of dense layouts. Previous works with layout migration [3,9] and cell synthesis [4,5,10] do not support layout generation for newer technology nodes bellow 130nm. Celltk [6] supports 90nm but presents a large area overhead compared to standard-cells.…”

Section: Introductionmentioning

confidence: 97%

A design flow for physical synthesis of digital cells with ASTRAN

Ziesemer

Reis

Moreira

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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As the foundries update their advanced processes with new complex design rules and cell libraries grow in size and complexity, the cost of library development become increasingly higher. In this work we present the methodology used in ASTRAN to allow automatic layout generation of cell libraries for technologies down to 45nm from its transistor level netlist description in SPICE format. It supports noncomplementary logic cells, allowing generation of any kind of transistor networks, and continuous transistor sizing. We describe our new generation flow which is currently being used to generate a library with more than 500 asynchronous cells in a 65nm process.

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Section: Introductionmentioning

confidence: 97%

A design flow for physical synthesis of digital cells with ASTRAN

Ziesemer

Reis

Moreira

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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show abstract

“…We believe our technique is flexible enough in order to be applied to other problems like compaction of nonstandard cells [8] and migration of digital [3] or analog [2] cells.…”

Section: Introductionmentioning

confidence: 98%

Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN

Ziesemer

Reis

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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This paper describes a technique to compact cell layouts efficiently using Mixed-Integer Linear Programming. By using binary variables we were able not only to model the conditional design rules, which apply to technology nodes down to 65nm, but also to compact layouts in the two-dimensions simultaneously. This technique was applied to a transistor network layout synthesis tool called ASTRAN which is being used to generate on-demand cells with unrestricted transistor network structure. We demonstrate in this paper that our technique is able to generate dense cell layouts, competitive with manually designed cells.

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Analog Layout Retargeting

Cited by 2 publications

References 28 publications

A design flow for physical synthesis of digital cells with ASTRAN

A design flow for physical synthesis of digital cells with ASTRAN

Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN

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