Analog macromodeling for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

Chary, S. Nagarjuna; Bushnell, M.L.

doi:10.1109/vlsid.2006.47

Cited by 4 publications

(2 citation statements)

References 18 publications

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“…Once the delay values (P D) for fault free paths (∀RO = 0) and faulty paths (∀RO ∈ ROs) are obtained, the longest path delays at each V DD of long paths (LP D G (V DD)) considering (T P ∈ T P s G ) and of short paths (LP D S (V DD)) considering (T P ∈ T P s S ) are identified using the fault free path delay data P D (∀RO = 0) as shown in line [19][20][21][22]. Once the delays of the faulty paths and the delays of the longest paths versus V DD are obtained, then it is possible to determine the model parameters.…”

Section: Fig 7 Prior Spectre Simulationmentioning

confidence: 99%

“…Given such dependencies, characterization and prediction of the behavior and thus the detectability with respect to voltage becomes difficult. Previous models [18], [19], [20], [21], [22] for resistive open faults did not explicitly account for V DD . Therefore for efficient multi-V DD fault detection and diagnosis, a voltage aware model which considers these dependencies has to be developed.…”

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confidence: 99%

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Multivoltage Aware Resistive Open Fault Model

Mohammadat

Ali

Hussin

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs and their behavior exhibits major dependencies on the supply voltage and test patterns. The widespread utilization of multiple supply voltages in contemporary VLSI designs poses a critical concern as to whether conventional models for resistive opens would still be effective. This is because conventional models do not explicitly model the VDD effect on fault behavior and detectability. Based on experimental analysis of ROFs in multi-VDD environment, we propose a voltage-aware model which divides the full range of open resistances (RO) into continuous behavioral intervals and three detectability ranges. The division of the behavior into intervals is based on monitoring the behavior change versus voltage across the resistance continuum, whereas the detectability ranges are based on finding minimum resistance for small and gross delay faults. It is highlighted that the detectable open resistance range is having a decreased trend with new technologies. Additionally it is shown that the observability of the unique increasing delay behavior with VDD for resistive open is reduced in new technologies. This poses reliability concerns and motivates the use of small delay testing for new technologies.

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Section: Fig 7 Prior Spectre Simulationmentioning

confidence: 99%

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confidence: 99%