Ahstract-Dynamic supply voltage scaling (DVS) is an efficient and practical design technique to reduce power consumption in VLSI devices. Due to the multiple volt age operating environment and the supply voltage depen dent behavior of physical faults, obtaining a minimal test set which gives the best fault coverage is challenging. Re searchers have showed that testing of resistive opens is best achieved at high supply voltage. However based on our ex perimental results on ISCAS-85 circuits it is shown that is not always the case for DVS enabled designs. This paper analyzes and identifies different detectability patterns for resistive open faults in such designs. Additionally it dis cussed the multi-VDD testing and its necessity to achieve 100% fault coverage.

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