Propagation of delay faults caused by resistive open faults with dynamic voltage scaling awareness

Abstract-Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs and their behavior exhibits major dependencies on the supply voltage and test patterns. The widespread utilization of multiple supply voltages in contemporary VLSI designs poses a critical concern as to whether conventional models for resistive opens would still be effective. This is because conventional models do not explicitly model the VDD effect on fault behavior and detectability. Based on experimental analysis of ROFs in multi-VDD environment, we propose a voltage-aware model which divides the full range of open resistances (RO) into continuous behavioral intervals and three detectability ranges. The division of the behavior into intervals is based on monitoring the behavior change versus voltage across the resistance continuum, whereas the detectability ranges are based on finding minimum resistance for small and gross delay faults. It is highlighted that the detectable open resistance range is having a decreased trend with new technologies. Additionally it is shown that the observability of the unique increasing delay behavior with VDD for resistive open is reduced in new technologies. This poses reliability concerns and motivates the use of small delay testing for new technologies.

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Multivoltage Aware Resistive Open Fault Model

Mohammadat

Ali

Hussin

et al. 2014

IEEE Trans. VLSI Syst.

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Propagation of delay faults caused by resistive open faults with dynamic voltage scaling awareness

Cited by 1 publication

References 18 publications

Multivoltage Aware Resistive Open Fault Model

Multivoltage Aware Resistive Open Fault Model

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