Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

“…It is worth pointing out that these NWs are almost square/-like, with sidewall height of 10 nm that is relatively small compared to the NW width (narrowest device is 17 nm-wide only). Therefore, the usually observed [39,83,92] Id (and gm) improvement with increase of NW (or Fin) width, related to the mobility improvement when conduction is dominated by the top-plane w.r.t sidewalls, almost does not appear in these devices featuring a complex 3D conduction. More details can be found in [56].…”

“…Their exploitation will be demonstrated on selected study cases of various advanced devices in wide temperature and frequency ranges, performed in our laboratory over the last years . In order to be complete, important works of other groups in the domain of device assessment for analog/RF applications are also listed [3,10,13,23,[79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95].…”

Performance of Source Follower Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

“…However, in ref. [14] it has been presented that the analog performance of strained FinFETs can be inferior to standard ones because of the larger channel length modulation effect degrading the g D , depending on the fin width. Standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the g D of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones.…”

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

“…Narrow triple gate FinFET transistors with fin width (W fin ) lower than 70 nm have particularly demonstrated to provide promising characteristics for digital [10] and analog applications [11][12][13][14]. The improved subthreshold slope (S), Early voltage (V EA ) and open-loop voltage gain (A V ) of these devices, which present a vertical channel covered by gate material forming a top and two 0038 sidewall gates, are firmly demonstrated in the literature with respect to the planar ones [12][13][14][15][16]. Also different studies about the harmonic distortion of triple FinFETs operating in saturation have recently been published showing their advantageous properties in comparison to single gate devices [17,18].…”