Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions

Lakshmikumar, K.R.

doi:10.1109/tcsii.2009.2019171

Cited by 21 publications

(5 citation statements)

References 7 publications

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“…The ring oscillator is composed of several gain-stage circuits [27]. In order to ensure that the oscillator can vibrate, in the case of small signals, the circuit needs a high loop gain.…”

Section: Circuit Design and Analysismentioning

confidence: 99%

Design and analysis of a low phase noise low power ring-VCO

Zou,

Zhang,

Cheng

et al. 2023

IEICE Electron. Express

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A low phase noise low power ring voltage-controlled oscillator (Ring-VCO) is proposed for phase-locked loops (PLLs) in the 802.11ah communication protocol band. A three-stage Ring-VCO with dual-path structure delay cells is designed to meet the high performance requirements of Internet of Things. The main noise source in the differential delay cell can be eliminated at the differential output, thus reducing phase noise. Implemented in an old TSMC 0.18 µm CMOS process, the Ring-VCO achieves a tuning range of 343.56-974.56 MHz. The phase noise at 1 MHz offset varies from -116.28 to -108.74 dBc/Hz, and the current consumed is 2.27 mA.

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“…The ring oscillator is composed of several gain-stage circuits [27]. In order to ensure that the oscillator can vibrate, in the case of small signals, the circuit needs a high loop gain.…”

Section: Circuit Design and Analysismentioning

confidence: 99%

Design and analysis of a low phase noise low power ring-VCO

Zou,

Zhang,

Cheng

et al. 2023

IEICE Electron. Express

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“…Ring oscillator is commonly used in the process technology development to characterize the process performance [6], [8], [13], [14]. It also widely uses as clock generator, voltage controlled oscillator [15]- [18] and phase locked loop [19], [20].…”

Section: Basic Concept Of Ring Oscillatormentioning

confidence: 99%

CMOS ring oscillator delay cell performance: a comparative study

Hadi¹,

Jidin²,

Wahab³

et al. 2019

IJECE

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A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.

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“…On the other hand, due to the absence of a tail transistor the output voltage swing is almost rail-to-rail, which is a very important feature that improves the phase noise with relatively low power consumption [11], [13]. The negative resistance of M p1+/-improves the CMRR because it produces high gain A d for differential signals.…”

Section: A Proposed Delay Elementmentioning

confidence: 99%

“…Differential topologies are more suitable for highspeed serial interfaces because they offer better commonmode and power supply rejection performance. However, pseudo-differential configurations [9] are even more suitable for such applications compared with their fully-differential counterparts [10] mainly due to low-voltage operation capability, extremely small chip area, high voltage swing and satisfactory low phase-noise performance in the cost of, relatively, small current dissipation [11], [12]. There are many RO design techniques with emphasis on minimizing the phase noise, increasing the oscillation frequency and the tuning range but with the penalty of increasing the power consumption [13].…”

Section: Introductionmentioning

confidence: 99%

A 3GHz VCO suitable for MIPI M-PHY serial interface

Demartinos

Tsimpos

Vlassis

et al. 2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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This paper proposes a VCO which is based on a pseudo-differential ring oscillator scheme and it is suitable for multi-Gbps serial interfaces. The ring oscillator topology is based on two CMOS inverters loaded by a simple negative resistance realized with pMOS transistors. The circuit performance is compliant with the MIPI Alliance M-PHY standard which is the most updated high-speed serial interface technology. The circuit is designed and simulated in a 65nm CMOS process with 1.2 V supply voltage. The frequency tuning range was 1.9 to 3.5 GHz with an almost constant K VCO equal to 5.7 GHz/V, approximately, while the current consumption was 6.4 mA at 3 GHz operating frequency and the phase noise was -94 dBc/Hz at 1 MHz frequency offset.

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Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions

Cited by 21 publications

References 7 publications

Design and analysis of a low phase noise low power ring-VCO

Design and analysis of a low phase noise low power ring-VCO

CMOS ring oscillator delay cell performance: a comparative study

A 3GHz VCO suitable for MIPI M-PHY serial interface

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