Analog property checkers: a DDR2 case study

Jones, Kevin D.; Konrad, Victor; Ničković, Dejan

doi:10.1007/s10703-009-0085-x

Cited by 17 publications

(7 citation statements)

References 22 publications

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“…Parametric signal temporal logic (PSTL) is based on the logic STL introduced in [17,21,18] for specifying and monitoring properties of real-valued continuous time signals, in particular those produced by analog circuits [13]. In the rest of the paper, we assume a time domain T = [0, ∞) (or a finite prefix of it) and traces (signals) of the form x : T → R n .…”

Section: Parametric Signal Temporal Logicmentioning

confidence: 99%

Parametric Identification of Temporal Properties

Asarin

Donzé

Maler

et al. 2012

Lecture Notes in Computer Science

129

144

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Abstract. Given a dense-time real-valued signal and a parameterized temporal logic formula with both magnitude and timing parameters, we compute the subset of the parameter space that renders the formula satisfied by the trace. We provide two preliminary implementations, one which follows the exact semantics and attempts to compute the validity domain by quantifier elimination in linear arithmetics and one which conducts adaptive search in the parameter space.

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Section: Parametric Signal Temporal Logicmentioning

confidence: 99%

Parametric Identification of Temporal Properties

Asarin

Donzé

Maler

et al. 2012

Lecture Notes in Computer Science

129

144

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“…al [22] proposed a very efficient monitoring algorithm for STL robustness, now implemented in the Breach [19] tool. The combination of robustness and sensitivity-based analysis of STL formulae have been successfully applied in several domains ranging from analog circuits [31] to systems biology [20,21], to study the parameter space and also to refine the uncertainty of the parameter sets. In the following we recall [23] the syntax and the quantitative semantics of STL that will be used in the rest of the paper.…”

Section: Stochastic Hybrid Automatamentioning

confidence: 99%

On the Robustness of Temporal Properties for Stochastic Models

Bartocci

Bortolussi

Nenzi

et al. 2013

Electron. Proc. Theor. Comput. Sci.

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Stochastic models such as Continuous-Time Markov Chains (CTMC) and Stochastic Hybrid Automata (SHA) are powerful formalisms to model and to reason about the dynamics of biological systems, due to their ability to capture the stochasticity inherent in biological processes. A classical question in formal modelling with clear relevance to biological modelling is the model checking problem. i.e. calculate the probability that a behaviour, expressed for instance in terms of a certain temporal logic formula, may occur in a given stochastic process. However, one may not only be interested in the notion of satisfiability, but also in the capacity of a system to mantain a particular emergent behaviour unaffected by the perturbations, caused e.g. from extrinsic noise, or by possible small changes in the model parameters. To address this issue, researchers from the verification community have recently proposed several notions of robustness for temporal logic providing suitable definitions of distance between a trajectory of a (deterministic) dynamical system and the boundaries of the set of trajectories satisfying the property of interest. The contributions of this paper are twofold. First, we extend the notion of robustness to stochastic systems, showing that this naturally leads to a distribution of robustness scores. By discussing two examples, we show how to approximate the distribution of the robustness score and its key indicators: the average robustness and the conditional average robustness. Secondly, we show how to combine these indicators with the satisfaction probability to address the system design problem, where the goal is to optimize some control parameters of a stochastic model in order to best maximize robustness of the desired specifications

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“…The STL/PSL specification language is a combination of STL [105] and PSL [1] with extensions to support checking analog properties. Amt has been used in case studies to verify properties of flash memory [121] and DDR2 DRAM [88] with varying levels of success.…”

Section: Lightweight Verificationmentioning

confidence: 99%

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Little¹,

Walter

Myers

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Analog circuit design is traditionally done by expert designers in an ad hoc manner heavily dependent on simulation. This methodology has worked successfully for many years, but process variation and design complexity are prompting designers to explore new techniques. Formal methods are being used successfully to aid in the complex validation problem for digital circuits. This dissertation presents formal methods for analog and mixed-signal (AMS) circuits. This dissertation describes the development of a formal model, labeled hybrid Petri nets (LHPNs), appropriate for the modeling and verification of AMS circuits. An LHPN is a Petri net variant capable of modeling both continuous and discrete quantities. Creating an LHPN model of an AMS circuit by hand is a complicated and error prone exercise that requires expert knowledge. This is unacceptable for practical adoption of the LHPN model and its associated analysis methods. For this reason, this dissertation introduces an automatic LHPN model generation method. The method uses a set of simulation traces and a desired system property to generate an LHPN modeling the behavior of the simulation traces. The model generator can also be used to generate abstract Verilog-AMS or VHDL-AMS models suitable for use in system-level simulations. Formal verification of a property over the entire state space of an LHPN model is complicated by the infinite state of the model. For this reason, the infinite states of the model are grouped into potentially finite groups of equivalent states for verification. Difference bound matrices (DBMs), a restricted form of convex polygons, are used to represent these equivalent classes of infinite states. Reachability analysis using DBMs is very efficient at the cost of exactness. This dissertation presents algorithms for conservative state space analysis and verification of LHPNs.Finally, these methods are demonstrated on several case studies of AMS circuits from both academia and industry. The formal verification methods demonstrate the ability to find bugs missed by standard simulations. The abstract modeling methods show the promise of using automatically generated abstract models by demonstrating up to 40x speedup for some examples.

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Analog property checkers: a DDR2 case study

Cited by 17 publications

References 22 publications

Parametric Identification of Temporal Properties

Parametric Identification of Temporal Properties

On the Robustness of Temporal Properties for Stochastic Models

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

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