Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Singh, Joginder; Jerome, C.; Wei, A.; Miller, R.L.; Bousquet, A.; Cheng, Lili; Zang, H.; Punchihewa, Kasun; Prabhu, Manjunatha; Senapati, B.; Kumar, Anil; Pandey, Shesh Mani; Iyer, Natarajan Mahadeva; Mittal, Anurag; Carter, Rick; Zhao, Lixia; Eller, M.; Samavedam, Srikanth

doi:10.1109/vlsit.2014.6894378

Cited by 12 publications

(3 citation statements)

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“…inFET transistors with outstanding electrical transport behavior in 14nm CMOS technology have been successfully demonstrated in high-volume production for low power and high performance applications [1]- [4]. High drive current combined with low power consumption, as well as simplified fabrication process with minimized impact on intrinsic silicon electrical properties have become mainstream in today's semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Hassan

Zhao

et al. 2020

IEEE J. Electron Devices Soc.

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FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of device Vtsat flavors is enabled in this experiment, presenting excellent device performances at different operating voltages of 0.55V, 0.8V and 1.2V. All results indicates that devices with no LDD and one less mask in FinFET architecture achieve lower cost, compelling performance and area scaling compared to devices with LDD, for high performance and low power applications.

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Section: Introductionmentioning

confidence: 99%

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Hassan

Zhao

et al. 2020

IEEE J. Electron Devices Soc.

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“…Back to 2016 AMD (Advanced micro device) present the 14 nm bulk FinFET [1]. They had shown the advantage of FinFET structure compare to the MOSFET such as the power consumption.…”

Section: Introductionmentioning

confidence: 99%

Effect of Temperature on 16 nm n-FiNFET

Pengchan

2018

KEM

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This research presents the effect of temperature that influence to the performance of 16 nm SOI n-FinFET structure. The structure has created with structure tool on GTS Framework. The transistor has 1 nanometer HfO2 gate oxide with all metal contact and biased on Minimos-NT tool, with variation of temperatures from 300 K to 420 K with 30 K per step. The result found the decrease in saturation current, threshold voltage and mobility. The temperature brought electron and rose the density of electron as the potential from power supply that energized to the structure. They made mobility fall with them rising. The temperature makes a performance of FinFET structure.

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“…They are placed close to the power lines to reduce high frequency noise. Recently there has been great progress on the development of high density (>20fF/µm 2 ) BEOL compatible MIM capacitors (1)(2)(3). However, no report has been published on the complexity of incorporating such MIM capacitors into the full integration scheme.…”

Section: Introductionmentioning

confidence: 99%

Topographic Complexities and Solutions for High Density BEOL MIM Capacitors

Cheng¹,

Kakita²,

Fox³

et al. 2017

ECS Trans.

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The BEOL compatible on-chip MIM capacitors have natural topography post MIM processing. In foundry manufacturing, design-related non uniform pattern density combined with MIM processing can lead to localized topographic process weak points. These weak points add further complexity and reduce the process window available to accommodate both MIM capacitors and Cu interconnections. The related fail modes include punch-through of MIM capacitors, un-landed Cu interconnection vias, and shorted Cu lines above the MIM capacitors. These challenges and complexities are described and characterized in this paper, as well as experiments and solutions to overcome these challenges. Manufacturing capability of BEOL MIM capacitors with capacitance density >20fF/µm 2 , leakage current density <100nA/cm 2 , and breakdown voltage > 5V has been demonstrated.

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Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Cited by 12 publications

References 0 publications

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node

Effect of Temperature on 16 nm n-FiNFET

Topographic Complexities and Solutions for High Density BEOL MIM Capacitors

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