Analog/RF wonderland: Circuit and technology co-optimization in advanced FinFET technology

Multi-Gate FinFET Mixer Variability Assessment Through Physics-Based Simulation

“…5 shows the contributions S + y + and S − y − of (5). Notice that for V G1 = 0.7 V the two values are nearly coincident, therefore, according to (5), the sensitivity is close to zero, while at V G1 = 0.6 V or V G1 = 0.8 V only partial cancellation is observed. Namely, with the 10 µm total periphery and assuming σ P of 10% with respect to the nominal fin width, (5) predicts σ G C of 14% for V G1 = 0.6 V and 16% at V G1 = 0.8 V, hence deteriorating significantly the stage conversion efficiency.…”

“…FinFETs have become the reference devices for digital applications, due to their reduced short channel effects, DIBL and smaller subthreshold slope. FinFETs are also competitive with UTB-SOI planar devices in terms of RF performance [3] and, even if concerns are raised for their larger parasitics, the full compatibility with CMOS digital applications fosters research on their AC characterization and modelling [3], [4] in the perspective of FinFET-based RF and mixed-mode circuit design [5]- [7]. While the typical FinFET is characterized by two (double gate) or even three (trigate) gates physically connected by a unique metalization, the possibility to exploit the multiple gates in an independent way (independent gates -IGs), is attractive for the possible development of novel circuit topologies [8]- [10], although it requires a more sophisticated technology to keep the gate metalizations apart [11].…”