Multi-Gate FinFET Mixer Variability Assessment Through Physics-Based Simulation

Bughio, Ahsin Murtaza; Guerrieri, Simona Donati; Bonani, Fabrizio; Ghione, Giovanni

doi:10.1109/led.2017.2717460

Cited by 19 publications

(5 citation statements)

References 20 publications

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“…The transconductance as given by equation (1) (𝑔 𝑚 -Input conductance) increments relatively with the linear gain in a gadget [3]. It connotes the variety in yield current with relating changes in input voltage 𝑉 𝑔𝑠 (Gate Voltage) when 𝑉 𝑑𝑠 (Drain Voltage) is kept unaltered [4].…”

Section: Results and Analysismentioning

confidence: 99%

“…These progressions are being embraced by different goliaths in the Chip and Semiconductor fabricating industry. Thusly in this research article, we have investigated the analog performance parameters of an Innovative Stacked Oxide Top-Bottom Gated (TBG) Junctionless (JL) FinFET [4]. The structure has been contrasted with the TBG-JL FinFET and a Traditional Junctionless FinFET structure to better glean the merits of the novel structure in terms of improved switching and reduced short channel effects.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Gangwani

Hajela

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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This paper depicts the analog investigation of a Novel Stacked Oxide Top Bottom Gated Junctionless (TBG-JL) Fin-shaped Field Effect Transistor (FinFET) structure. The structure is designed in this way to enhance the switching performance and curtail the Short Channel Effects (SCEs). The study is done on Silvaco Atlas TCAD tools for the Novel Stacked Oxide FinFET device and analyzed against Top-Bottom Gated Junctionless FinFET and Traditional FinFET. The Novel device shows 280 times improvement in switching ratio when stacked against the Traditional JL FinFET at identical gate length at room temperature (300K). The results from device simulation affirm that the Novel device has better analog performance over Traditional Junctionless FinFET and diminishes the Short Channel Effects (SCEs) a cut above the Traditional Junctionless FinFET.

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Section: Results and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Gangwani

Hajela

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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“…Next, we extend this analysis to the Split-Gate (SPG) devices shown in Figure 2a, taking advantage of the versatility of the proposed platform. This type of structures are appealing for non-linear applications, such as mixers [34], or to implement different functionalities, such as logic gates, with a reduced number of transistors [35]. For the sake of relevance, we limit the investigation to tensile n-type and compressive p-type conduction.…”

Section: Resultsmentioning

confidence: 99%

Multi-scale modeling of 2D GaSe FETs with strained channels

Toral-López¹,

Santos²,

Marín³

et al. 2021

Nanotechnology

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Electronic devices based on bidimensional materials (2DMs) are the subject of an intense experimental research, that demands a tantamount theoretical activity. The latter must be hold up by a varied set of tools able to rationalize, explain and predict the operation principles of the devices. In the broad context of multi-scale computational nanoelectronics, there is currently a lack of simulation tools connecting atomistic descriptions with semi-classical mesoscopic device-level simulations and able to properly explain the performance of many state-of-the-art devices. To contribute to filling this gap we present a multi-scale approach that combines fine-level material calculations with a semi-classical drift-diffusion transport model. Its use is exemplified to assess 2DM-FET devices with strained channels, showing great potential to capture the changes in the crystal structure and their impact into the device performance. Interestingly, we verify the capability of strain in monolayer GaSe to enhance the conduction of one type of carrier, enabling the possibility to mimic the effect of chemical doping on 2D materials. These results illustrate the great potential of the proposed approach to connect levels of abstraction rarely connected before and thus contribute to the theoretical modeling of state-of-the-art 2DM-based devices.

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“…To sustain the scaling down of complementary metal-oxide-semiconductors (CMOS), new materials and structures have been continuously incorporated into the design and manufacturing of CMOS devices, such as High-κ/metal gate (HKMG) [1][2][3], strain technology [4][5][6], and multi-gate transistors [7][8][9][10]. For the past 50 years, CMOS devices have evolved from planar transistors with micron-level channel lengths to gate-all-around (GAA) transistors with sub-twenty nanometer channel lengths [11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Sun,

Chen,

Zhang

et al. 2024

Micromachines

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With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

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Multi-Gate FinFET Mixer Variability Assessment Through Physics-Based Simulation

Cited by 19 publications

References 20 publications

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Multi-scale modeling of 2D GaSe FETs with strained channels

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

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