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In this work, we have designed a Novel Top-Bottom Gated Junctionless (JL) Fin-Shaped Field Effect Transistor (FinFET) Structure. The main idea of designing this structure is to improve the output efficiency and reduce the Short Channel Effects (SCEs). This paper analyzes the Analog Performance of a Novel Junctionless FinFET Structure with 5nm Gate length investigated on Silvaco Atlas Technology Computer Aided Design (TCAD) Tools and compared to Conventional Junctionless Bulk FinFET Structure. This Novel JL FinFET has gates on both sides of the substrate, hence the name Top-Bottom Gated (TBG) FinFET. It is determined that the proposed novel device enhances the switching ratio by almost 100 times, hence improving the transconductance and output current. Our device also shows improvement in the output conductance over the conventional JL FinFET. The simulation results show that the Novel TBG JL FinFET structure has better ION/IOFF and thus reduces the short channel effects than the conventional bulk FinFET more effectively.

This paper depicts the analog investigation of a Novel Stacked Oxide Top Bottom Gated Junctionless (TBG-JL) Fin-shaped Field Effect Transistor (FinFET) structure. The structure is designed in this way to enhance the switching performance and curtail the Short Channel Effects (SCEs). The study is done on Silvaco Atlas TCAD tools for the Novel Stacked Oxide FinFET device and analyzed against Top-Bottom Gated Junctionless FinFET and Traditional FinFET. The Novel device shows 280 times improvement in switching ratio when stacked against the Traditional JL FinFET at identical gate length at room temperature (300K). The results from device simulation affirm that the Novel device has better analog performance over Traditional Junctionless FinFET and diminishes the Short Channel Effects (SCEs) a cut above the Traditional Junctionless FinFET.

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