Lower Fin Modulation Analysis for a Novel 5nm Top Bottom Gated Junctionless FinFET for improved performance

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

“…280 times improvement in switching ratio is observed for the Innovative Stacked Oxide FinFET structure when stacked against Traditional JL FinFET at 300K [1]. Further, enhanced analog performance is observed for the Innovative Stacked Oxide FinFET structure in terms of Transconductance and Transconductance Generation Factor when stacked against the other two devices [2]. Thus the device is an excellent choice for Analog Performance at Room Temperature (300K) and helps in diminishing Short Channel Effects a notch better.…”

“…Various headways are being designed to achieve precisely that. This trend of downsizing the devices to achieve more portability and efficiency starting right from MOSFET devices till SOI and FinFET helps in developing far more capable devices which are handheld at the same time [2]. But reducing the device dimension comes at a cost.…”

“…Additionally it upgrades the gate controllability of the gadget when stacked against the TBG JL FinFET [2].…”

“…As we increase the doping concentration of the device, more charge carriers are available and hence the device exhibits better output current for same gate voltage as shown in Figure 5 and similarly the Transconductance which varies directly with Output current increases as well as portrayed in Figure 6. The Top-Bottom Gated FinFET devices have fins on both sides of the oxide layer and thus have more device heights than the Traditional JL FinFET structure [2]. The Novel FinFET structure and TBG JL FinFET have device heights of 33nm due to presence of lower fin.…”