Analog statistical simulation

Rencher, M.

doi:10.1109/cicc.1991.164109

Cited by 9 publications

(6 citation statements)

References 7 publications

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“…One common characteristic of current prediction algorithms is the use of multivariate normal (or multinormal) distributions to model process variation, with many authors choosing the same four supposedly independent parameters for MOSFET devices: length, width, gate oxide thickness, and flatband voltage [3]- [8]. Others have preferred to use manufacturing parameters such as diffusion times and temperatures [9], [10]. Often, correlation is eliminated through the use of principal component analysis [11], [12], but even this results in an underlying distribution which is normal.…”

Section: Introductionmentioning

confidence: 99%

Using multivariate nested distributions to model semiconductor manufacturing processes

Gibson

Poddar²,

May

et al. 1999

IEEE Trans. Semicond. Manufact.

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This paper demonstrates the advantages of modeling semiconductor process variability using a multivariate nested distribution. This distribution allows estimation not only of correlation among various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer-to-wafer, lot-to-lot, etc.). This permits matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching. The technique also provides focus for process improvement efforts into those areas with the maximum potential reward. Test structures have been designed and fabricated to facilitate extraction of the parameters for the multivariate nested distribution. Using data from a sample of these structures, a process model is built and analyzed. Monte Carlo techniques are then employed using SPICE and a probabilistic process model to predict the performance of a multiplying digital-to-analog converter (MDAC), and the results are compared to measured data from fabricated circuits. Simulations performed using a model built using the multivariate nested approach are shown to provide superior results when compared to simulations using currently accepted multivariate normal models.

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Section: Introductionmentioning

confidence: 99%

Using multivariate nested distributions to model semiconductor manufacturing processes

Gibson

Poddar²,

May

et al. 1999

IEEE Trans. Semicond. Manufact.

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“…Input variables are often examined using analysis of variance (ANOVA) techniques [2] to eliminate statistically insignificant parameters [3], [4]. Uncorrelated multinormal distributions are often used, with many authors choosing the same four supposedly independent parameters for MOSFET devices: length, width, gate oxide thickness, and flatband voltage [5]- [10].…”

Section: Introductionmentioning

confidence: 99%

Statistically based parametric yield prediction for integrated circuits

Gibson

Poddar

May

et al. 1997

IEEE Trans. Semicond. Manufact.

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This paper presents a novel procedure for predicting integrated circuit parametric performance and yield when provided with sample transistor test results and a circuit schematic. Two enhancements to the existing Monte Carlo simulation procedures are described: 1) a multivariate nested model is used to reproduce random process-induced device variations, rather than the multivariate multinormal model typically used, and 2) the stochastic Monte Carlo method for mapping process variability into a performance distribution is replaced with a deterministic mapping technique. The use of multivariate nested distributions allows estimation not only of correlation between various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer to wafer, lot to lot, etc.). This allows matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching, and provides focus for process improvement efforts into those areas with the maximum potential reward. The use of deterministic mapping provides simulation results which are repeatable and do not rely on chance to insure that the process parameter space has been evenly explored. A software package which implements the entire procedure has been written in C++.

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“…Today, there is strong economic pressure to use statistical device models. These models allow simulations to be run not only at any process "comer" (for example, at the 2 sigma or 3 sigma level), but also enable the use of more powerful Design for Manufacturability applications [7,8].…”

Section: Development Of the Performance Variation Modelmentioning

confidence: 99%

A method for modeling the manufacturability of IC designs

Boskin¹,

Spanos²,

Korsh³

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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A methodology for modeling the manufacturability of MOS transistors and circuits has been developed. The models are based on a small set of measurable process characterization parameters, whose variation explains the range of performance seen during production. A statistical MOSFET model, based on these measurable process parameters, was developed using global optimization and regression modeling of key fitting parameters to accurately predict transistor characteristics over a wide range of process variation. These same process parameters can be measured on the manufacturing floor, both in-line and at electrical test, and used to predict the performance of the fabricated integrated circuit before packaging and final test. The models for use in manufacturing and design are integrated, and data taken from the manufacturing line can be used to identify process shifts as well as to suggest design improvements for manufacturability enhancement. IntroductionIn today's competitive semiconductor manufacturing environment, it is important to be able to anticipate the effects of processing variation while still designing the product, and to characterize and control this variation while producing it [1,2]. In this work we present a methodology for modeling IC performance in terms of a simple set of process characterization data. First, a MOSFET model is developed, which utilizes a set of process parameters to predict transistor performance across the range of process variation seen on the fabrication line. At the design stage, the MOSFET model can be used for statistical circuit simulation in order to test the manufacturability of the design. These parameters can also be measured during production, and used to predict the performance of fabricated parts, early in the production cycle. A compact, product-specific performance prediction model is built from a combination of simulation results and manufacturing data. The prediction model can be used with production data for process control and production planning.This method has been applied on a commercial 1 Mbit EPROM fabricated in a 1.5 pm CMOS process.This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry. There are several reasons for this problem which are addressed in this research.First, early work in statistical modeling relied heavily on the use of process simulation, with the accompanying prohlem of tuning the simulator to match an actual manufacturing line [6]. The method presented in this work does not rely on process simulation, but uses data collected from transistor characterization, in conjunction with straightforward device physics. Further, the use of manufacturing data ensures that the parameters are measurable using production line capable techniques, and that they explain most of the variation seen on an actual fab line.Secondly, the early statistical device models were verified by matching a...

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Analog statistical simulation

Cited by 9 publications

References 7 publications

Using multivariate nested distributions to model semiconductor manufacturing processes

Using multivariate nested distributions to model semiconductor manufacturing processes

Statistically based parametric yield prediction for integrated circuits

A method for modeling the manufacturability of IC designs

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