Analog‐to‐Digital Conversion in the Early Twenty‐First Century

Abstract

Analog‐to‐digital converters (ADCs) continue to be important components of signal‐processing systems, such as those for mobile communications, software radio, radar, satellite communications, and others. This article revisits the state‐of‐the‐art of ADCs and includes recent data on experimental converters and commercially available parts. Converter performances have improved significantly since previous surveys were published (1999–2005). Specifically, aperture uncertainty (jitter) and power dissipation have both decreased substantially during the early 2000s. The lowest jitter value has fallen from approximately 1 picosecond in 1999 to < 100 femtoseconds for the very best of current ADCs. In addition, the lowest values for the IEEE Figure of Merit (which is proportional to the product of jitter and power dissipation) have also decreased by an order of magnitude. For converters that operate at multi‐GSPS rates, the speed of the fastest ADC IC device technologies e.g., InP, GaAs, is the main limitation to performance; as measured by device transit‐time frequency, f T , has roughly tripled since 1999. ADC architectures used in high‐performance broadband circuits include pipelined (successive approximation, multistage flash) and parallel (time‐interleaved, filter‐bank) with the former leading to lower power operation and the latter being applied to high‐sample rate converters. Bandpass ADCs based on delta‐sigma modulation are being applied to narrow band applications with ever increasing center frequencies. CMOS has become a mainstream ADC IC technology because it enables designs with low power dissipation and it allows for significant amounts of digital signal‐processing to be included on‐chip. DSP enables correction of conversion errors, improved channel matching in parallel structures, and provides filtering required for delta‐sigma converters. Finally, a performance projection based on a trend in aperture jitter predicts 25 fs in approximately 10 years, which would imply performance of 12 ENOB at nearly 1‐GHz bandwidth.

Photonic ADC: overcoming the bottleneck of electronic jitter

“…Note that the scheme with N channels not only increases the sample rate by N, but also reduces the required analog bandwidth of photodetectors and electronic ADCs [24], which need to be only as high as several times the original laser repetition rate to avoid intersymbol interference between subsequent pulses. Importantly, because of reduced analog bandwidth at the input of electronic ADCs, the impact of comparator ambiguity -another major factor limiting accuracy at high frequencies [4] -is completely eliminated. Fig.…”

“…inability of ADCs to sample at precisely defined times. Figure 1 shows ENOB as a function of input frequency for high-performance electronic ADCs, as reviewed by Walden [4], including some ADCs that have appeared afterwards. Dashed lines represent limits on ENOB due to jitter.…”

“…Dashed lines represent limits on ENOB due to jitter. The best electronic ADCs deliver jitter levels of 60-80 fs in the 100-400 MHz frequency range; reducing the jitter further becomes increasingly difficult, especially beyond gigahertz frequencies, and if the past is a good prediction for the future, it will take nearly a decade to improve the jitter performance by an order of magnitude [4]. As discussed below, ultra-stable mode-locked laser sources with jitter levels many orders of magnitude lower exist today; if used for sampling, they could improve ADC performance by orders of magnitude.…”

Progress in Photonic Analog-to-Digital Conversion

“…At the post-processing stage, the samples captured in different wavelength channels are interleaved and distortion-compensated to obtain the final digital representation of the RF signal. Note, that the scheme with N channels reduces the required analog bandwidth of photodetectors and electronic ADCs in proportion to N, which means that the comparator ambiguity -a major limiting factor at high frequencies [8] -becomes a non-issue. (b) a vision for the photonic ADC implemented as a single electronic-photonic silicon chip [7].…”

“…The progress in electronic ADC performance is facing two major challenges: aperture jitter of the sampling clock and comparator ambiguity [8]. In the photonic approach, the problem of aperture jitter is addressed by sampling the RF signal optically with ultra-stable pulse trains available from mode-locked lasers; the timing jitter of such pulse trains can approach few attoseconds [9][10][11][12], which is over four orders of magnitude less than the jitter in state-of-the-art electronic ADCs [8]. The second challengecomparator ambiguity -is completely eliminated by separating the fast RF signal into multiple slower channels, using a time- [13] or a wavelength-demultiplexing [14][15][16] scheme.…”