Analog-to-stochastic converter using magnetic-tunnel junction devices

Onizawa, Naoya; Katagiri, Daisaku; Gross, Warren J.; Hanyu, Takahiro

doi:10.1145/2770287.2770303

Cited by 13 publications

(7 citation statements)

References 18 publications

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“…However, the digital units to generate unary bitstreams are more expensive compared to the analog counterparts. There exist explorations into the low-cost conversion of analog signals into rate-coded bitstreams for image processing applications [3,17,30,38,63], i.e., analog-to-stochastic conversion. Onizawa et al leverage Magnetic-Tunnel Junction (MTJ) devices [63], whose state switching is probabilistic.…”

Section: Analog-to-stochastic Conversionmentioning

confidence: 99%

“…There exist explorations into the low-cost conversion of analog signals into rate-coded bitstreams for image processing applications [3,17,30,38,63], i.e., analog-to-stochastic conversion. Onizawa et al leverage Magnetic-Tunnel Junction (MTJ) devices [63], whose state switching is probabilistic. With proper congurations, a rate-coded bitstream with its value linear to the analog input amplitude can be generated, eliminating the need for digital hardware.…”

Section: Analog-to-stochastic Conversionmentioning

confidence: 99%

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uBrain

Pan

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Brain computer interfaces (BCIs) have been widely adopted to enhance human perception via brain signals with abundant spatialtemporal dynamics, such as electroencephalogram (EEG). In recent years, BCI algorithms are moving from classical feature engineering to emerging deep neural networks (DNNs), allowing to identify the spatial-temporal dynamics with improved accuracy. However, existing BCI architectures are not leveraging such dynamics for hardware eciency. In this work, we present uBrain, a unary computing BCI architecture for DNN models with cascaded convolutional and recurrent neural networks to achieve high task capability and hardware eciency. uBrain co-designs the algorithm and hardware: the DNN architecture and the hardware architecture are optimized with customized unary operations and immediate signal processing after sensing, respectively. Experiments show that uBrain, with negligible accuracy loss, surpasses the CPU, systolic array and stochastic computing baselines in on-chip power eciency by 9.0⇥, 6.2⇥ and 2.0⇥. CCS CONCEPTS• Hardware ! Emerging interfaces; Application specic integrated circuits; • Computing methodologies ! Specialpurpose algebraic systems; Articial intelligence.

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Section: Analog-to-stochastic Conversionmentioning

confidence: 99%

Section: Analog-to-stochastic Conversionmentioning

confidence: 99%

uBrain

Pan

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…There are several ways of transforming analog data into stochastic numbers. ASC presented in [16] performs the conversion with MTJ, which consumes less power than BSC with the same precision but is incompatible with standard CMOS technology. Thus an energy efficient CMOS ASC is proposed here.…”

Section: Analog To Stochastic Converter(asc)mentioning

confidence: 99%

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing

Zhang

Wang

Zhang

et al. 2019

2019 International Conference on IC Design and Technology (ICICDT)

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Convolutional neural network (CNN) achieves excellent performance on fascinating tasks such as image recognition and natural language processing at the cost of high power consumption. Stochastic computing (SC) is an attractive paradigm implemented in low power applications which performs arithmetic operations with simple logic and low hardware cost. However, conventional memory structure designed and optimized for binary computing leads to extra data conversion costs, which significantly decreases the energy efficiency. Therefore, a new memory system designed for SC-based multiply-accumulate (MAC) engine applied in CNN which is compatible with conventional memory system is proposed in this paper. As a result, the overall energy consumption of our new computing structure is 0.91pJ, which is reduced by 82.1% compared with the conventional structure, and the energy efficiency achieves 164.8 TOPS/W. I.

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“…The CMOS/MTJ hybrid circuits are analyzed with Cadence Virtuoso. In order to achieve linear characteristic between MTJ operation current and stochastic probability, MTJ write duration is set up at 5 ns [22].…”

Section: A Stochastic Behavior Of Mtjmentioning

confidence: 99%

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction

Naviner

Cai

Wang

et al. 2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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Stochastic Computing (SC) with random bit streams has been used to replace binary radix encoding. SC-based logic cicuits take advantage of area minimization, fast and accurate operation and inherent fault tolerance. In this paper, the stochastic characteristics inherent in Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) bring on an innovative stochastic number generator (SNM) circuit. The hybrid MOS-MTJ process allows to design a 4T1M structure SNM with 1.98μm*1.46μm layout area, using 28 nm ultra thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. A case study of designed SNM is performed by polynomial function synthesis, which significantly reduces area. The proposed circuit also takes advantage of non-volatility and infinite endurance from STT-MTJs, which can be applied to reliability-aware circuits and systems 1 .

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Analog-to-stochastic converter using magnetic-tunnel junction devices

Cited by 13 publications

References 18 publications

uBrain

uBrain

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction

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