Analogue fault simulation based on layout dependent fault models

Closing the gap between analog and digital

“…Hard fault modeling and simulation which addresses analog and mixed-signal circuits have been a subject of many publications [1], [2], [6], [7], and [8]. In [1] it has been suggested that the faulty analog behavior should be modeled as a modification to the nominal macromodel.…”

“…In [8] to enable the circuit fault-effects to be simulated in a reasonable simulation time, behavioral models of each circuit block were developed. Hybrid fault simulations were performed by replacing each circuit block with its behavioral model equivalent except the block that has a target fault inserted.…”

“…Indeed, instead of testing for the upper and lower resistance values for faults as in [8] (Table 1), in our case, fault dominance will be used where only the least dominating resistance (the largest) will be tested for shorts, and the least denominating resistance (the smallest) will be tested for open circuits.…”

“…R fault are stored in fault dictionary. Table 1 presents a list of circuit defects and the corresponding typical resistance range obtained by statistical analysis of circuit defects [8]. R fault is compared to R typical .…”

A design for testability study on a high performance automatic gain control circuit

“…The resulting layout extracted fault list contains several kinds of shorts (inter-node, inter-resistor or shorts affecting multiple nets) and opens. The main advantage of this fault list is that a weighted fault coverage (WFC), taking the fault probability into account, can be computed and difficult to detect faults can be related to certain layout structures 38,39 . To enable fault simulation prior to layout, the re-use of DfT optimised cells and their corresponding layout extracted fault list is a promising compromise.…”