Analysing the operation of the basic pass transistor structure

Abstract

SUMMARYPass transistor logic has become important for the design of low-power high-performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters.

Gaussian pulse approximation using standard CMOS and its application for sub‐GHz UWB impulse radio

“…However, it has high complexity due to the presence of the short-circuit current, which acts parasitically on the output waveform. A simplified version of Bisdounis's model was proposed in [25,26]. It 'translates' the effect of short-circuit current into a time shift to the output waveform.…”

“…produces almost the same result as Bisdounis's model for most regions. The analytical expression is summarized as follows, more details about the above two models can be found in [24][25][26].…”

Input mapping algorithm for parallel transistor structures

“…Normalized inputs are required to solve the differential equations describing the circuit operation [1,[4][5][6]. Parallel transistors, of the same width, with normalized inputs can be replaced by one transistor that has the normalized ramp as input while its width is equal to the sum of the widths of the parallel transistors [7]. However, real signals are almost never normalized and an algorithm is needed to map real signals to equivalent normalized ramps, which are mathematically tractable.…”

BDD‐based synthesis for mixed CMOS/PTL logic

“…For example, the variable s associated with the node in Figure 1(b) is the control signal in the multiplexer in Figure 1(a). Pass‐transistor logic (PTL) has the capability to implement a logic function with a smaller number of transistors and less power dissipation, and several studies on realizing circuits with PTL have been published 1–4, showing that this technology is viable. Unfortunately, a function may require BDD representation of exponential size if it is mapped onto PTL 5.…”