Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting

An Integrated Piezoelectric Energy Harvesting Interface Circuit with Adaptive S3BF Control

“…It would reduce the power efficiency, and is essential in some low-voltage applications. Fortunately, the IR drop of the diodes can be reduced by active rectifiers [5], [6], [7]. Some optimized interface circuits have been proposed to reduce the energy-loss by charging or discharging CP more quickly.…”

“…Some optimized interface circuits have been proposed to reduce the energy-loss by charging or discharging CP more quickly. The synchronized switch harvesting on inductor (SSHI) circuit, which employed LC resonance to flip the voltage across CP momentarily during zero-crossing, was adopted to reduce charge loss thus improve power conversion efficiency [4], [5], [6], [8]. Unfortunately, the reported SSHI control circuit is sensitive to the process, voltage and temperature (PVT) variations, which causes the timing errors.…”

“…Unfortunately, the reported SSHI control circuit is sensitive to the process, voltage and temperature (PVT) variations, which causes the timing errors. As a result, the charge will flow back to the CP and the harvesting efficiency is degraded [6]. In that case, the off-chip trimming techniques, e.g., digital control [4] or variable resistors [8], are often adopted to compensate these timing errors.…”

“…Besides, the SSHI circuits are also often sensitive to the parasitic resistance of the inductor and LC resonant loop, so that a large inductance is needed in many applications (e.g., 0.82 mH in [4] and 3.3 mH in [8]). To avoid the use of large inductors so as to decrease the volume of the entire systems, multi-step bias-flip becomes much more attractive since it makes the circuit less sensitive to those parasites, mainly owing to the decrease of the transient current of the inductor [3], [6]. Hence, a small inductor e.g., 47 μH [6] or inductorless bias-flip schemes can also be implemented [9], [10].…”

“…To avoid the use of large inductors so as to decrease the volume of the entire systems, multi-step bias-flip becomes much more attractive since it makes the circuit less sensitive to those parasites, mainly owing to the decrease of the transient current of the inductor [3], [6]. Hence, a small inductor e.g., 47 μH [6] or inductorless bias-flip schemes can also be implemented [9], [10]. However, too many steps not only greatly increase the design complexity, but also increase the risk of timing errors and overlong flipping time, which may also cause severe flipping loss as stated in [10].…”