Analysis and Design of a 17-GHz All-<i>npn</i> Push-Pull Class-C VCO

Veni, Simone; Andreani, Pietro; Caruso, Michele; Tiebout, M.; Bevilacqua, Andrea

doi:10.1109/jssc.2020.2991512

Cited by 15 publications

(3 citation statements)

References 21 publications

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“…When we deal with real implementations, though, the class-C oscillator may have an edge, albeit not a large one [21]. Finally, since BJT transistors cannot be allowed to enter saturation, the class-C topology is definitely very attractive for BJT oscillators [22].…”

Section: Phase Noisementioning

confidence: 99%

Harmonic Oscillators in CMOS—A Tutorial Overview

Andreani

Bevilacqua

2021

IEEE Open J. Solid-State Circuits Soc.

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The harmonic oscillator is a truly irreplaceable as well as ubiquitous analog integrated circuit. Starting from the basics of its CMOS implementation, we will discuss the phase noise of the harmonic oscillator in some detail, where the intrinsic large-signal operation mandates a time-variant analysis. This will be followed by a survey of the most popular design techniques enabling a low phase noise and a wide range of oscillation frequencies.INDEX TERMS Oscillator, harmonic, phase noise, tuning range, CMOS.

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Section: Phase Noisementioning

confidence: 99%

Harmonic Oscillators in CMOS—A Tutorial Overview

Andreani

Bevilacqua

2021

IEEE Open J. Solid-State Circuits Soc.

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“…Differing from conventional parallel connected multi-core oscillators based on extra coupling circuit, the circular-type multi-core oscillators [25], [26], [27], [28], [29] are attractive for high area efficiency. Compared with mm-wave single-core oscillators [31], [32], whose inductors may suffer the destructive coupling between traces, the larger diameter of the circular-type oscillator helps to obtain a higher quality factor. However, once the core number is increased, complex supply and decoupling networks are required [29].…”

Section: Introductionmentioning

confidence: 99%

Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance

Shu,

Luo

2023

IEEE J. Solid-State Circuits

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In this article, a scalable inter-core-shaping multicore oscillator is proposed to achieve low phase noise and high figure of merit (FoM) at millimeter-wave (mm-wave) band. Adjacent NMOS and PMOS cores generate common-mode (CM) resonance simultaneously, but with opposite signs; thus, differential capacitors can be used to create resonance at twice the oscillation frequency. Such a CM resonance limits flicker noise upconversion and reduces phase noise. The capacitors in differential mode (DM) and CM are all differential, which avoids the degradation of quality factor caused by the single-end capacitor. Besides, the magnetic coupling among the cores only operates in DM. In CM, the negative and positive mutual couplings cancel each other, which increases the CM inductance and its quality factor. Moreover, the topology shows low sensitivity to the parasitics in the return path and the mismatch among the cores, which makes it suitable for the massive-core extension. The 28-GHz quad-core and 20-core circuits are prototyped in a conventional 40-nm CMOS process. Occupying a core area of 0.06 mm 2 , the quad-core oscillator achieves 1-MHz FoM of 193.3 dBc/Hz. The 20-core circuit exhibits 1-MHz phase noise of −120.8 dBc/Hz at 28 GHz and 1-MHz FoM of 192.7 dBc/Hz. Index Terms-Figure of merit (FoM), figure-of-merit area (FoM A ), inter-core shaping, low phase noise, millimeter wave (mm wave), multi-core, oscillator.

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“…Actually, due to the phase noise deterioration caused by larger size varactors and switchedcapacitor banks, most single-core VCOs can hardly achieve the more-than-30% bandwidth. [8][9][10][11][12] Although transform-based dual-band VCOs have been explored in Ref. [13][14][15][16], the tuning ranges are still not enough.…”

Section: Introductionmentioning

confidence: 99%

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.

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Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO

Cited by 15 publications

References 21 publications

Harmonic Oscillators in CMOS—A Tutorial Overview

Harmonic Oscillators in CMOS—A Tutorial Overview

Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

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