Harmonic Oscillators in CMOS—A Tutorial Overview

Andreani, Pietro; Bevilacqua, Andrea

doi:10.1109/ojsscs.2021.3109854

Cited by 11 publications

(3 citation statements)

References 70 publications

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“…The coarse-tuning unit with a 13-MHz LSB uses a resistor-biased structure [78], as shown in Fig. 10(b), for enhancing the Q-factor and lowering parasitics.…”

Section: Switched-capacitor Banks and I/q Imbalance Sourcesmentioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90 • I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140-250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors' knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

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“…The coarse-tuning unit with a 13-MHz LSB uses a resistor-biased structure [78], as shown in Fig. 10(b), for enhancing the Q-factor and lowering parasitics.…”

Section: Switched-capacitor Banks and I/q Imbalance Sourcesmentioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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“…9 Generally, the resonate frequency is determined by the system, and output amplitude is limited by the process. 10 In this design, the 28 nm process is adopted and the high voltage device 25OD33 is used for design to maximize amplitude. It is difficult to further improve the phase noise with these two parts.…”

Section: Vco Designmentioning

confidence: 99%

“…The phase noise of the VCO is mainly determined by inductor Q value, resonate frequency and output amplitude 9 . Generally, the resonate frequency is determined by the system, and output amplitude is limited by the process 10 . In this design, the 28 nm process is adopted and the high voltage device 25OD33 is used for design to maximize amplitude.…”

Section: Architecture and Designmentioning

confidence: 99%

A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

Zhao,

Zhang,

Zhang

et al. 2023

Micro & Optical Tech Letters

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This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

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