Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS

Testa, Paolo Valerio; Carta, Corrado; Jorges, Udo; Ellinger, Frank

doi:10.1109/jssc.2018.2797240

Cited by 24 publications

(10 citation statements)

References 15 publications

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“…Moreover, the cascode reduces the Miller effect. These three characteristics improve the amplifier frequency response towards high frequencies [17].…”

Section: A Cssdamentioning

confidence: 99%

“…Balun, mixer, LO driver and CSSDA are designed to operate at the same bias potentials annotated in Fig. 1, while a multi-plate capacitors as in [17] have been used to route the bias voltages from the DC pads till the transistors. Although the four bias voltages could be generated on chip form a common external voltage supply, one pad per bias voltage was added to have independent control during the experimental characterizing.…”

Section: Receiver Architecture Analysis and Designmentioning

confidence: 99%

“…Finally, with the amplifier being the basic block of transceivers, mixers and other key system parts can be derived from it. The receiver front-end presented in this work makes use of a cascaded single-stage distributed amplifier (CSSDA) [11], [17], [18], [19] optimized for low noise as the first stage of the receiver chain. A single-balanced mixer, with a transconductance stage based on distributed-amplifier techniques and inductive peaking, is then used for the frequency translation of the received signal.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz

Testa

Riess

Carta

et al. 2021

IEEE Open J. Circuits Syst.

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This work presents a direct-conversion receiver for G-band applications formed by a cascaded single-stage distributed amplifier optimized for low noise, a single-balanced active mixer with inductive peaking and broadband RF matching, and a local oscillator (LO) driver. The receiver is optimized for reduced DC and LO power consumption, while practical levels of linearity and noise are retained. Prototypes of the complete receiver and of the stand-alone mixer are implemented in 0.62 mm 2 and 0.39 mm 2 of a 130 nm SiGe BiCMOS technology with 450 GHz maximum-oscillation frequency. The measured receiver saturated gain in LO compression is 17 dB with a 6 dB band of 60 GHz and a 3 dB band of 30 GHz, while the input power which compresses the gain by 1 dB (P in1dB ) is −35 dBm. The simulated receiver double-sideband noise figure is 11 dB. Finally, the circuit requires an LO power of −17 dBm at 170 GHz and a DC power of 98 mW. The measured gain of the mixer is −13 dB with a 3 dB band of 70 GHz. The component P in1dB is −20 dBm for −18 dBm LO power and 53 mW DC power. These circuits offer one of the largest operation bandwidth together with one of the lowest DC and LO power consumption against the state of the art.

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“…Moreover, the cascode reduces the Miller effect. These three characteristics improve the amplifier frequency response towards high frequencies [17].…”

Section: A Cssdamentioning

confidence: 99%

Section: Receiver Architecture Analysis and Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz

Testa

Riess

Carta

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

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“…N = 1), G DA is limited by g m , which is quite low for high f T devices. The issue of limited gain has been addressed through multiplicative DA topologies -formed from cascading or arranging SSDAs in a matrix [9], [10], [16], [19], [24], [28]- [30].…”

Section: Merit Of the Ssda And The M-ssda Formentioning

confidence: 99%

InP DHBT Single-Stage and Multiplicative Distributed Amplifiers for Ultra- Wideband Amplification

Odedeyi

Giannakopoulos

Zirath

et al. 2020

IEEE Trans. Circuits Syst. I

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This paper highlights the gain-bandwidth merit of the single stage distributed amplifier (SSDA) and its derivative multiplicative amplifier topologies (i.e. the cascaded SSDA (C-SSDA) and the matrix SSDA (M-SSDA)), for ultra-wideband amplification. Two new monolithic microwave integrated circuit (MMIC) amplifiers are presented: an SSDA MMIC with 7.1 dB average gain and 200 GHz bandwidth; and the world's first M-SSDA, which has a 12 dB average gain and 170 GHz bandwidth. Both amplifiers are based on an Indium Phosphide DHBT process with 250 nm emitter width. To the authors best knowledge, the SSDA has the widest bandwidth for any single stage amplifier reported to date. Furthermore, the three tier M-SSDA has the highest bandwidth and gain-bandwidth product for any matrix amplifier reported to date.

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“…where N is the number of stages (which is unity for the SSDA), g m is the transconductance of the active device, and Z o−in and Z o−out are the image impedances of the input and output transmission lines, respectively. The issue of limited gain has been addressed through multiplicative DA topologies -formed from cascading or arranging SSDAs in a matrix [5]- [8], [11]- [13], such that the gain of the multiplicative DA (G mDA ) is given by…”

Section: Merit Of the Ssda And Multiplicative Da Formentioning

confidence: 99%

Single-Stage and Multiplicative Distributed Amplifiers for 200GHz+ Amplification

Odedeyi

Giannakopoulos

Zirath

et al. 2019

2019 IEEE Asia-Pacific Microwave Conference (APMC)

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In this paper, we review the merit of the single stage distributed amplifier (SSDA) and consider the potential of its derivative multiplicative amplifier topologies (the cascaded and the matrix SSDA) for ultra-wideband amplification. We highlight the significant bandwidth advantage that the SSDA topology offers and the higher gain potential of multiplicative DAs compared to the conventional multi-stage DA. Furthermore, we describe how available design trade-offs may be used to offset inherent noise performance limitations of this family of distributed amplifiers. We also report a new SSDA MMIC with 7.1 dB gain at 200 GHz bandwidth and a high frequency gain tuning range of 5 dB to 12 dB, based on an Indium Phosphide DHBT process with 250 nm emitter width.

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Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS

Cited by 24 publications

References 15 publications

A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz

A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz

InP DHBT Single-Stage and Multiplicative Distributed Amplifiers for Ultra- Wideband Amplification

Single-Stage and Multiplicative Distributed Amplifiers for 200GHz+ Amplification

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