Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9–14.3-GHz 85-fs-rms Jitter PLL

Wang, Yizhuo; Shi, Jiahe; Xu, Hao; Ji, Shujiang; Mao, Yiyun; Zou, Tenghao; Tao, Jun; Min, Hao; Yan, Na

doi:10.1109/jssc.2023.3242617

Cited by 7 publications

(1 citation statement)

References 25 publications

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“…Subsampling PLL (SSPLL) is promising to achieve low in-band phase noise without divider [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37]. The intrinsically high gain of the subsampling phase detector (SSPD) can suppress in-band phase noise significantly.…”

mentioning

confidence: 99%

A 21.8–41.6-GHz Low Jitter and High FoM$_{\bm{j}}$ Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

Chen,

Shu,

Yin

et al. 2024

IEEE Trans. Microwave Theory Techn.

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In this article, a wideband millimeter-wave (mm-wave) fast-locking subsampling phase-locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM j ) is proposed. A quadrature subsampling phase detector (QSSPD)-based dead zone automatic controller (DZAC) is introduced for fast locking. Such DZAC eliminates the long locking time caused by the dead zone of frequency-locked loop (FLL) while maintaining low in-band phase noise of subsampling loop (SSL). The mm-wave quad-mode oscillator is integrated in the FL-SSPLL to achieve a wide frequency range. The proposed FL-SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.18 mm 2 . Measurements exhibit a wide output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The FL-SSPLL achieves a 62.7-79.1-fs root-mean-square (rms) jitter across the whole frequency range. The total power consumption is 18.3-23.6 mW, leading to FoM j from −248.3 to −251.4 dB. Meanwhile, the FL-SSPLL features a robust lock acquisition and achieves less than 1.5-µs locking time.

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