Analysis and Design of a 5G Multi-Mode Power Amplifier using 130 nm CMOS technology

Mansour, Marwa; Zekry, Abdelhalim; Ali, Mohammed K.; Shawkey, Heba

doi:10.1109/isqed51717.2021.9424284

Cited by 3 publications

(3 citation statements)

References 7 publications

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“…Nevertheless, the consumption power of 716 mW is very high for this kind of application. Similar to our PA, a reported work [20] designed differential class-F modes under two blocs (Driver + Power stage); the saturated efficiency was 29.5% for a saturated output power of 23 dBm and a power gain of 24 dB. The circuit was totally integrated and implemented over a chip area of 0.53 mm 2 , which seems acceptable.…”

Section: Layout Of the Designed Class-f Power Amplifiersupporting

confidence: 52%

“…Moreover, other reported works have shown the impact of drain waveform shaping on reducing the dissipative power. Mansour, in [20], designed a multi-mode linear (class-AB)/switching (class-F) double-stage cascode PA with an output network constituting of a second-third harmonics network and a series matching network. This structure was mainly employed to drive both sinusoidal and square input signal forms.…”

Section: Introductionmentioning

confidence: 99%

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Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

et al. 2023

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This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)B, 19 dB (+ 5 dB)B and 45% (+ 5% to 10%)B, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a 732×605 μm2 chip’s surface. (B: indicates the improved values in the power back-off region).

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Section: Layout Of the Designed Class-f Power Amplifiersupporting

confidence: 52%

Section: Introductionmentioning

confidence: 99%

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

et al. 2023

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“…(A) Normalized amplitude drains current harmonic elements at direct conversion (DC),

f_{o}

, and

3 f_{o}

versus the conduction angle (α) 34,35 and (B) simplified diagram of the suggested PA and principle of third harmonics cancellation…”

Section: Power Amplifier Analysis and Designmentioning

confidence: 99%

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Mansour

2022

Circuit Theory & Apps

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High‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA) and power combiner for millimeter‐wave applications using 130 nm CMOS technology are presented in the paper. The suggested PA uses transformer coupled for input, inter‐stage, and output matching networks where the inter‐stage matching inductors are utilized to enhance the RF performance. The proposed power amplifier is composed of three stages: first, driver, and power stages. The first stage operates in a class‐C to improve the efficiency and decrease power dissipated while a class‐AB is used in the driver and power stages to maximize the output power. The proposed PA and power combiner designs are suitable for mm‐wave 5G applications. The coupling transformers, inter‐stage matching inductors, and output combiner are analyzed and designed using Ansoft high‐frequency structure simulator (HFSS) and achieve high‐quality factor and high‐coupling coefficient over the frequency range from 26 to 33 GHz. The proposed three‐stage transformer‐coupled power amplifier covers a frequency band from 26 GHz to 33 GHz with a saturated output power of 13.1 dBm, a peak power added efficiency (PAE) equals 19.1%, and a maximum power gain of 13.25 dB. Whereas the proposed power combiner has a saturated output power of 16.3 dBm, a maximum PAE equals 20.5% and a peak gain of 16.5 dB. The proposed three‐stage transformer‐coupled PA and power combiner consume low power of 65 mW and 128 mW, respectively. Moreover, the adjacent channel power ratios (ACPR) of the proposed PA and power combiner equal −30 dBc and −36 dBc, respectively, for 20 MHz channel bandwidth. Finally, the active areas of the proposed power amplifier and power combiner equal 0.25 mm2 and 0.69 mm2, respectively, while the chip areas are 0.55 mm2 and 1 mm2, respectively.

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DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

Mansour

2023

AEU - International Journal of Electronics and Communications

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Analysis and Design of a 5G Multi-Mode Power Amplifier using 130 nm CMOS technology

Cited by 3 publications

References 7 publications

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

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