Analysis and experimental verification of digital substrate noise generation for epi-type substrates

Heijningen, M. van; Compiet, J.; Wambacq, Piet; Donnay, S.; Engels, M.; Bolsens, I.

doi:10.1109/4.848209

Cited by 125 publications

(55 citation statements)

References 12 publications

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“…One example is the computationally extensive approach where digital circuit blocks are simulated directly together with an extracted substrate network (4,5). While this approach may lead to accurate results it involves lengthy and time-consuming simulations.…”

Section: Chaptermentioning

confidence: 99%

“…A lumped element circuit model describing the electrical characteristics of the substrate is also given in the figure. Unlike heavily doped substrates, where the substrate can be treated as a single node, lightly doped bulk substrates have to be modeled using a resistive network representation (4)(5)(6). The Nwell is, however, still modeled as a single node owing to its comparatively higher conductivity than the bulk.…”

Section: Chaptermentioning

confidence: 99%

“…7.3.1, the switching noise generated by digital circuits can propagate through the substrate to reach sensitive analog/RF circuits and deteriorate their performance. A number of methods have been proposed for achieving an efficient model that is able to capture the main features of the switching noise (4)(5)(6)(7)(12)(13)(14)(15)(16)(17)(18). For heavily doped substrates the substrate is simplified as one electrical node due to their low resistivity, and switching noise modeling methods using this simplification have been proposed (13,14).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Modelling of Substrate Noise and Mitigation Schemes for UWB Systems

Shen

Mikkelsen

Larsen

2012

Microwave and Millimeter Wave Circuits and Systems

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Section: Chaptermentioning

confidence: 99%

Section: Chaptermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Modelling of Substrate Noise and Mitigation Schemes for UWB Systems

Shen

Mikkelsen

Larsen

2012

Microwave and Millimeter Wave Circuits and Systems

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“…These substrate contacts give low impedance from the digital ground to the substrate surface. Hence the SSN is injected in the substrate region of the digital circuit and spread through the substrate to other circuits, thereby degrading performance in analog circuits [9], [10]. The SSN is one of the main sources of noise in digital integrated circuits [11], [12].…”

mentioning

confidence: 99%

Reduction of Substrate Noise in Sub Clock Frequency Range

Sherazi

Asif

Backenius³

et al. 2010

IEEE Trans. Circuits Syst. I

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Abstract-We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.Index Terms-Flip-flops, integrated circuit noise, mixed analogdigital integrated circuits, simultaneous switching noise, substrate noise.

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“…Due to decreasing feature sizes, increasing clock frequencies, lower supply voltages, and larger interconnect parasitics, the digital portions of a mixed-signal chip become much noisier and often interfere with sensitive analog and RF circuitry. Therefore, it is a challenging task to design high-speed mixed-signal and RF ICs and substrate noise coupling becomes a key issue that must be considered for SoC applications [1], [2], [3], [17].…”

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confidence: 99%