Silencer! A tool for substrate noise coupling analysis

Birrer, P.; Fiez, T.S.; Mayaram, K.

doi:10.1109/socc.2004.1362367

Cited by 10 publications

(5 citation statements)

References 12 publications

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“…These methods have been implemented in the Cadence DFII environment and Silencer! [14] to provide a seamless tool for substrate noise coupling analysis. With the process outlined in this paper, characterizing a substrate for pre-and post-layout noise coupling simulations can be done in a simple and efficient manner without the need for pre- …”

Section: Discussionmentioning

confidence: 99%

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates

Peterson

Mayaram

Fiez

2007

2007 IEEE Custom Integrated Circuits Conference

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An automated process, requiring the fabrication of only a few simple test structures, can efficiently characterize a silicon substrate by extracting the process constants of a Z-parameter based macromodel. The resulting model is used to generate a resistive substrate network that can be used in noise coupling simulations. This process has been integrated into the Cadence DFII environment to provide a seamless substrate noise simulation package which alleviates the need for precharacterized libraries.

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Section: Discussionmentioning

confidence: 99%

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates

Peterson

Mayaram

Fiez

2007

2007 IEEE Custom Integrated Circuits Conference

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“…The connections from the circuit to substrate networks were determined with the use of Silencer! [8]. All equivalent package, bondwire, and PCB parasitics were also included in the final simulation.…”

Section: Simulation Methodologymentioning

confidence: 99%

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry

Hanken

Held

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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A pseudo-random number generator implemented in asynchronous logic generates one-fifth the RMS substrate noise compared to the equivalent design in synchronous logic. An asynchronous 8051 processor generates one-third the RMS substrate noise as the equivalent synchronous design. The SNR of a second order delta-sigma modulator (DSM) is not affected by substrate noise due to an asynchronous processor while it experiences 15 dB degradation when the synchronous 8051 processor is clocked near integer multiples of the DSM sampling frequency.

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“…The path the substrate noise will travel depends on the doping profile of the substrate, the spacing between the substrate ports, shape/area of the ports, and whether or not the backplane is floating. The substrate network can be extended for any arbitrary number of substrate ports [29]. Fig.…”

Section: A Silencer! Inputs and Outputsmentioning

confidence: 99%

“…user interface have been described in [24], [29] and The Models & Options window is shown in Fig. 7.…”

Section: A Description and Simulation Of A Simple Examplementioning

confidence: 99%

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Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

Birrer

Arunachalam

Held

et al. 2006

IEEE Trans. Circuits Syst. I

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This paper presents an approach to reduce substrate cross-talk noise between noisy and sensitive circuitry in mixed-signal integrated circuits at different stages of design and layout development. Silencer! a new, fully automated, schematic-driven substrate noise coupling analysis tool is introduced to accomplish this task. The tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. Two different methods, fast scalable macro-models and a boundary element solver are integrated into Silencer!. These methods allow extractions of a substrate network from geometric layout information. Simulation results obtained with Silencer! are accurate to within 10% of measured integrated circuits.Index Terms-Coupling noise, integrated circuit noise, mixed-signal noise, noise analysis tool, noise minimization, pre-/post-layout analysis, substrate noise, substrate noise analysis, supply noise.

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Silencer! A tool for substrate noise coupling analysis

Cited by 10 publications

References 12 publications

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates

Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

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