Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

Birrer, P.; Arunachalam, Sasi Kumar; Held, Martin; Mayaram, K.; Fiez, T.S.

doi:10.1109/tcsi.2006.885689

Cited by 6 publications

(2 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A schematic based analysis methodology has been proposed in [9] to reduce the number of elements obtained from the postlayout extraction process. The transistor level simulation of a large-scale circuit including the back annotation of the substrate resistance of every port, however, is not feasible for large-scale circuits due to the nonlinear nature of the device models.…”

Section: A Existing High Level Substrate Noise Analysis Approachesmentioning

confidence: 99%

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Salman

Jakushokas

Friedman

et al. 2009

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.Index Terms-Ground noise, high level analysis methodology, mixed-signal ICs, substrate coupling noise, substrate extraction, substrate noise analysis.

show abstract

Section: A Existing High Level Substrate Noise Analysis Approachesmentioning

confidence: 99%

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Salman

Jakushokas

Friedman

et al. 2009

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…N THE ERA of increasing integration, the technological advancements have lead us to integrate not only digital circuits of high device density, but also analog circuits on the same die [1], [2]. The circuit speed and the number of devices have increased because of the downscaling in device sizes.…”

mentioning

confidence: 99%

Reduction of Substrate Noise in Sub Clock Frequency Range

Sherazi

Asif

Backenius³

et al. 2010

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.Index Terms-Flip-flops, integrated circuit noise, mixed analogdigital integrated circuits, simultaneous switching noise, substrate noise.

show abstract