Analysis and implementation of a new soft switching DC/DC PWM converter

Abstract

This study presents a new DC/DC converter with series-connected transformers to achieve zero voltage switching (ZVS) for power switches, less transformer secondary winding and partial ripple current cancellation. Two three-level circuits using the same active switches are operated with interleaved half switching cycle. The voltage stress of all switches is clamped at V in /2. The transformers secondary windings are connected in series to balance the primary side currents. The current-doubler rectifier is adopted on the output side. Thus, the output inductor ripple currents can be partially cancelled each other and the resultant ripple current at the output capacitor is reduced compared with the output ripple current of the centre-tapped rectifier topology. Based on the resonant behaviour by the output capacitance of active switches and the leakage inductance (or external inductance), all power switches are turned on at ZVS. Laboratory experiments with a 1 kW prototype, verifying the effectiveness of the proposed converter, are described.

A review of power electronics equipment for all-electric ship MVDC power systems

“…However, the basic structure to which most of the other structures are inspired is the one introduced in [139] and shown in Fig. 14. Many of the converters have the NPC input stage endowed with a flying capacitor [140][141][142][143]148,[150][151][152][154][155][156][157][158]160,162]. Most of the input stages are composed of a single leg, but some of them have two [153,156,159,163] or three [147,149] legs.…”

Soft switching DC/DC converter with high voltage gain and less current ripple

“…It is clear that the ZVS condition of the lagging-leg switches is more difficult to be implemented. Based on the derived primary inductance L r in (36) and the ZVS conditions (13) and (27), the minimum ZVS load condition of the lagging-leg switches is expressed in (37). Because two output inductor currents are equal to I o /2, the output inductances L o1 and L o2 are derived as:…”

PV-Transformer-Less Inverter Topology for Battery-Equivalent DC Supply from Leakage Current

“…Though having reduced the overall cost and size, such transformer-less configurations suffer from the inherit issues of leakage current. The reduction of leakage current has been addressed for human safety and power-loss reason in [9]- [11]. Leakage current minimization is also a point being addressed in the IC designs and some of the proposed techniques are those suggesting power gating technique, CMOS design technique, RBB technique, Dual-Vt and DualTox, bit line leakage current compensation technique [10]- [12].…”