Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits

Heck, Guilherme; Heck, Leandro S.; Singhv, Ajay; Moreira, Matheus T.; Beerel, Peter A.; Calazans, Ney

doi:10.1109/vlsid.2015.60

Cited by 15 publications

(17 citation statements)

References 18 publications

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“…As an illustration of such research efforts, Heck [15] developed a PhD Thesis where the focus was obtaining a single programmable delay element to support the design of asynchronous BD circuits resilient to timing errors. This was in fact the culmination of a joint research between a research group at the University of Southern California in USA and the authors' research group, which had previously generated research results on several aspects of DE design for BD circuits [16]- [19]. Specifically addressed design aspects in the cited publications are analysis and optimization of programmable DEs, studies on how fine-grained and coarse-grained delay adjustments perform in practice, and to control the effect of voltage variations over the delay-matching characteristic of DEs.…”

Section: A Primer On Asynchronous Circuitsmentioning

confidence: 99%

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Calazans

Rodolfo

Sartori

2021

JICS

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades, but their costs are increasingly hard to cope with. Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes. This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process variations; (3) temperature variations; (4) circuit aging. Besides addressing energy-efficiency and all the mentioned robustness aspects, this work also approaches some of the state-of-the-art tools available to deal with asynchronous design, and points to desirable research development to be conducted in these subjects in the future.

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Section: A Primer On Asynchronous Circuitsmentioning

confidence: 99%

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Calazans

Rodolfo

Sartori

2021

JICS

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“…There are many ways to implement the control logic [13]; using burst-mode specifications has been explored in [12]. In addition, there are many ways to design delay lines, as the authors and others explore in [14]. However, ensuring these have their proposed delay during P&R, when gate sizing, wire delay, and cross-couping capacitance play a role is non-trivial.…”

Section: Cad Flow Challenges and Opportunitiesmentioning

confidence: 99%

A path towards average-case silicon via asynchronous resilient bundled-data design

Beerel

Calazans

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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The periodic nature of the global clock in traditional synchronous designs forces circuits to be margined for the worst possible case of process, voltage, temperature, and data conditions. This constrains the silicon to operate at worst-case frequencies and at conservative supply voltages. Resilient architectures promise to remove these margins, by detecting and correcting timing errors when they occur, thereby creating the potential to achieve real average-case operation. However, synchronous resilient schemes previously proposed can suffer from multiple issues, including being susceptible to metastability and requiring often complex changes to the architecture to support replay-based recovery from timing errors. These problems respectively lead to circuit failures and/or incur high timing penalties when errors occur. This paper reviews a recently proposed asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. It also describes some open issues and new research opportunities this template presents, including automation problems to target average-case operation, specific circuit optimizations to minimize resiliency overhead, and the need for new test procedures to tune delay lines and screen out bad chips.

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“…By changing the number of pMOSs that are forward body biased, the current changes and hence the delay of the whole structure. The inverting structure is replicated to make the DE rise and fall delays match, an important characteristic for two‐phase asynchronous design [12].…”

Section: Proposed Architecturementioning

confidence: 99%

2 ps resolution, fine‐grained delay element in 28 nm FDSOI

2015

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A novel diversely body-biased current-starved delay element (DE) architecture for fine-grained DEs is presented. Using fully depleted silicon-on-insulator back-body biasing, it achieves a resolution of 2 ps with a delay quantisation error of 7.1%. Compared with the state-ofthe-art DEs, it exhibits the least leakage current and efficient overall energy consumption and is the most robust to process variations.

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Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits

Cited by 15 publications

References 18 publications

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

A path towards average-case silicon via asynchronous resilient bundled-data design

2 ps resolution, fine‐grained delay element in 28 nm FDSOI

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