Disaster robotics has become a research area in its own right, with several reported cases of successful robot deployment in actual disaster scenarios. Most of these disaster deployments use aerial, ground, or underwater robotic platforms. However, the research involving autonomous boats or Unmanned Surface Vehicles (USVs) for Disaster Management (DM) is currently spread across several publications, with varying degrees of depth, and focusing on more than one unmanned vehicle—usually under the umbrella of Unmanned Marine Vessels (UMV). Therefore, the current importance of USVs for the DM process in its different phases is not clear. This paper presents the first comprehensive survey about the applications and roles of USVs for DM, as far as we know. This work demonstrates that there are few current deployments in disaster scenarios, with most of the research in the area focusing on the technological aspects of USV hardware and software, such as Guidance Navigation and Control, and not focusing on their actual importance for DM. Finally, to guide future research, this paper also summarizes our own contributions, the lessons learned, guidelines, and research gaps.

The use of robotics in disaster scenarios has become a reality. However, an Unmanned Surface Vehicle (USV) needs a robust navigation strategy to face unpredictable environmental forces such as waves, wind, and water current. A starting step toward this goal is to have a programming environment with realistic USV models where designers can assess their control strategies under different degrees of environmental disturbances. This paper presents a simulation environment integrated with robotic middleware which models the forces that act on a USV in a disaster scenario. Results show that these environmental forces affect the USV’s trajectories negatively, indicating the need for more research on USV control strategies considering harsh environmental conditions. Evaluation scenarios were presented to highlight specific features of the simulator, including a bridge inspection scenario with fast water current and winds.

We present the design and analysis of three commonly used types of programmable delay elements suitable for use in 2-phase bundled-data asynchronous circuits. Our objective is to minimize power consumption and delay margins needed for correct operation under voltage scaling. We propose both circuit design and transistor sizing strategies to optimize these elements and discuss the relative trade-offs observed in a 65 nm bulk CMOS technology.

This paper proposes an adaptive pulse generator using Pulse Amplitude Modulation (PAM). The circuit was implemented with eight Pulse Generator Units (PGUs) to produce up to eight monocycles per pulse. The number of monocycles per pulse is inversely proportional to the Power Spectrum Density (PSD) bandwidth in the Impulse Radio Ultra-Wide Band (IR-UWB). The complete circuit contains two pulse generator blocks, each one composed by eight PGUs to build a rectangular waveform at the output. The PGU has been implemented with Edge Combiners High (ECH) and Edge Combiners Low (ECL) to encode the information. Each Edge Combiner has a high impedance circuit that is selected by digital control signals. The circuit has been simulated, showing an output pulse amplitude of ≈70mV for the high logic level and an amplitude of ≈35mV for the low logic level, both at 100 MHz Pulse Repetition Frequency (PRF). This produces a mean pulse duration of ≈270ps, a mean central frequency of ≈3.7GHz and a power consumption less than 0,22µW. The pulse generator block occupies an area of 0.54mm 2 .

The correct functionality of quasi-delay-insensitive asynchronous circuits can be jeopardized by the presence and propagation of transient faults. If these faults are latched, they will corrupt data validity and can make the whole circuit to stall, given the strict event ordering constraints imposed by handshaking protocols. This is particularly concerning for the delay-insensitive minterm synthesis logic style, widely adopted by asynchronous designers to implement combinatory quasi-delay-insensitive logic, because it makes extensive use of C-elements and these components are rather vulnerable to transient effects. This paper demonstrates that this logic style submits C-elements to their most vulnerable states during operation. It accordingly proposes the alternative use of the delay-insensitive maxterm synthesis for hardening QDI circuits against transient faults. The latter is a logic style based on the return-to-one 4-phase protocol. Although this style also relies on extensive usage of C-elements, the states where these components are most vulnerable are avoided. Results display improvements of over 300% in C-elements tolerance to transient faults, in the best case.