Analysis and optimization of ring oscillator using sub-feedback scheme

Huang, Hong-Yi; Tsai, Fu-Chien

doi:10.1109/ddecs.2009.5012093

Cited by 2 publications

(5 citation statements)

References 6 publications

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“…In case C, the DCO adopts the first loop circuit to increase the operational frequency by 234%. Hence, case C is popular for use in multi-phase and high speed oscillators [11]. In cases D and E, the second loop and RB-DL can extend the highest operational frequency by 9% and 2%, respectively.…”

Section: Circuit Implementationmentioning

confidence: 99%

“…It usefully increases operational frequency with multi-phase outputs. They also analyzed an n-stage ring oscillator with 3-stage sub-feedback loops [11]. The block diagram of MP-DCO is illustrated in Fig.…”

Section: B Proposed Mp-dco With 3-stage Sub-feedback Schemementioning

confidence: 99%

“…The sub-feedback loop technique for PLL as analog type was proposed in [11]. It usefully increases operational frequency with multi-phase outputs.…”

Section: B Proposed Mp-dco With 3-stage Sub-feedback Schemementioning

confidence: 99%

“…The second method uses a phase interpolator [10], whose circuit improves the phase resolution. The third approach uses an oscillator with a k-stage sub-feedback loop to increase operational frequency and generate multi-phase outputs [11]. It also operates at a low supply voltage as a gigahertz oscillator with multi-phase outputs.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, a multi-phase clock is useful for a receiver. Three useful methods for multi-phase outputs have been disused in [9,10,11]. First, the conventional scheme uses an inverter chain, which is easy to implement, but its operational frequency depends on the number of stages in the inverter chain [9].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

Liu

Cheng

et al. 2016

IEICE Electron. Express

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This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm 2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.

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Section: Circuit Implementationmentioning

confidence: 99%

Section: B Proposed Mp-dco With 3-stage Sub-feedback Schemementioning

confidence: 99%

“…The sub-feedback loop technique for PLL as analog type was proposed in [11]. It usefully increases operational frequency with multi-phase outputs.…”

Section: B Proposed Mp-dco With 3-stage Sub-feedback Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

Liu

Cheng

et al. 2016

IEICE Electron. Express

View full text Add to dashboard Cite

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A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

Liu

2021

IEEE Access

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An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper. The bootstrapped ring oscillator can boost the output voltage to a higher level than the supply voltage. Thus, the oscillator can be operated in low-supply-voltage applications. MOS varactor is used in the bootstrapped capacitor to reduce the area cost. Circuit analysis and simulated verification were performed for an optimized design. The interpolated DCO has multiphase outputs and a high operating frequency. The test chip was implemented in a 90-nm CMOS process, and the core area was 60 × 117 μm 2. The power consumptions at 1160 MHz and 20 MHz were 912.6 μW (at 0.6 V) and 2.94 μW (at 0.2 V), respectively. In the worst-case jitter performance, the root mean square (RMS) jitters were less than 0.42%. INDEX TERMS Bootstrapped, digitally controlled oscillator (DCO), interpolation, multiphase, phaselocked loop (PLL).

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Analysis and optimization of ring oscillator using sub-feedback scheme

Cited by 2 publications

References 6 publications

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

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