This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm 2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.

A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from − 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and − 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm 2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

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A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18 µm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 µm × 75 µm and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/ • C from 0 to 100 • C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of −102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.

An AC stress test was performed to investigate the accompanying electronic effects in a HfO2 resistive random access memory during the SET transition, which featured a sudden decrease in resistance. Comparing the DC and AC measurement results indicated the pronounced influence of interrupted stress on both the mean values and variations of time to SET. First-principles calculations suggested that the charge states (+2, +1, or neutral) of oxygen vacancies affect the migration barrier for forming oxygen vacancy clusters. Therefore, a charge-state-dependent SET model is proposed to include the additional electronic effects induced by the dynamics of electron trapping and detrapping in oxygen vacancies during AC stress. A trimodal Weibull fitting based on the proposed model reproduced the experimental time to SET distributions obtained in a wide range of AC stress conditions.