Analysis and optimization of variable-latency designs in the presence of timing variability

The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

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Analysis and optimization of variable-latency designs in the presence of timing variability

Cited by 3 publications

References 21 publications

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs

An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations

Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

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