Analysis and performance exploration of high performance (HfO₂) SOI FinFETs over the conventional (Si₃N₄) SOI FinFET towards analog/RF design

Abstract

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs (short channel effects) in sub 22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2 (conventional HfO2 spacer SOI FinFET) and device-D3 (source/drain extended HfO2 spacer SOI FinFET) over the device-D1 (conventional Si3N4 spacer SOI FinFET) at 20 nm technology node through the 3-D (dimensional) simulation process. The major performance parameters like Ion (ON current), Ioff (OFF current), gm (transconductance), gd (output conductance), AV (intrinsic gain), SS (sub-threshold slope), TGF = gm/Id (trans-conductance generation factor), VEA (early voltage), GTFP (gain trans-conductance frequency product), TFP (tans-conductance frequency product), GFP (gain frequency product), and fT (cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation, device-D3 and D2 give better results in terms of gm, ID (drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of fT, GTFP, TFP, and GFP parameters both at low and high values of VDS = 0.05 V and VDS = 0.7 V respectively.

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

“…Another, two RF parameters like gain frequency product (GFP) and gain transconductance frequency product (GTFP) [41] against gate voltage have been shown in Fig. 6c&6d respectively.…”

Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications

“…The major challenges in nanoscale devices are short channel effects (SCEs) and stringent process requirements for formation of abrupt p-n junctions, which, limits their applicability for analog/RF applications [4]- [7]. The non-classical CMOS device structures, such as, underlap IM-DGFETs features high immunity to SCEs due to larger effective channel length (L eff ) [8].…”