Analysis and Validation of Low-Frequency Noise Reduction in MOSFET Circuits Using Variable Duty Cycle Switched Biasing

Abstract

Randomization of the trap state of defects present at the gate Si-SiO2 interface of MOSFET is responsible for the low-frequency noise phenomena such as Random Telegraph Signal (RTS), burst, and 1/f noise. In a previous work, theoretical modelling and analysis of the RTS noise in MOS transistor was presented and it was shown that this 1/f noise can be reduced by decreasing the duty cycle (fD) of switched biasing signal. In this paper, an extended analysis of this 1/f noise reduction model is presented and it is shown that the RTS noise reduction is accompanied with shift in the corner frequency (fc) of the 1/f noise and the value of shift is a function of continuous ON time (Ton) of the device. This 1/f noise reduction is also experimentally demonstrated in this paper using a circuit configuration with multiple identical transistor stages which produces a continuous output instead of a discrete signal. The circuit is implemented in 180 nm standard CMOS technology, from UMC. According to the measurement results, the proposed technique reduces the 1/f noise by approximately 5.9 dB at fs of 1 KHz for 2 stage, which is extended up to 16 dB at fs of 5 MHz for 6 stage configuration. arXiv:1704.00876v1 [cond-mat.other]

1/$f$ Noise Reduction Using In-Pixel Chopping in CMOS Image Sensors

“…The measurement setup is shown in Fig. 4(b) and is similar to that reported in [6]. The measured noise PSD of the DUT for varying frequency span of 100 Hz, 800 Hz, and 100 kHz is shown in Fig.…”

“…The measurement setup for the low-frequency noise is shown in Fig. 5(c), which is similar to that reported in [8], [10], [27]. The low noise voltage preamplifier (SR560) is used to amplify the noise power of the DUT.…”

“…In ( 2) and (3), it is assumed that the chopping frequency is much higher than the low-frequency noise corner frequency and the noise pairs like N sf,A (t 1 ) and N sf,A (t 2 ) are correlated due to high f ch [5], [6].…”

“…This technique is commonly used in many systems like phase locked loop (PLL), in which switching is used to reduce the phase noise of a voltage controlled oscillator (VCO). In [9], [10] the switching of MOS transistor is shown to reduce the 1/f noise in APS using shared source followers among the pixels. However, in this technique, the noise reduction is limited by the number of shared source followers.…”

“…The 1/f noise reduction technique in [2] and [3] needs process modifications and thus, would increase the cost. The cycling of a MOS transistor between strong inversion and accumulation also reduces 1/f noise [4]- [6].…”