Randomization of the trap state of defects present at the gate Si-SiO2 interface of MOSFET is responsible for the low-frequency noise phenomena such as Random Telegraph Signal (RTS), burst, and 1/f noise. In a previous work, theoretical modelling and analysis of the RTS noise in MOS transistor was presented and it was shown that this 1/f noise can be reduced by decreasing the duty cycle (fD) of switched biasing signal. In this paper, an extended analysis of this 1/f noise reduction model is presented and it is shown that the RTS noise reduction is accompanied with shift in the corner frequency (fc) of the 1/f noise and the value of shift is a function of continuous ON time (Ton) of the device. This 1/f noise reduction is also experimentally demonstrated in this paper using a circuit configuration with multiple identical transistor stages which produces a continuous output instead of a discrete signal. The circuit is implemented in 180 nm standard CMOS technology, from UMC. According to the measurement results, the proposed technique reduces the 1/f noise by approximately 5.9 dB at fs of 1 KHz for 2 stage, which is extended up to 16 dB at fs of 5 MHz for 6 stage configuration. arXiv:1704.00876v1 [cond-mat.other]

Randomization of the trap state of defects present at the gate Si-SiO 2 interface of MOSFET is responsible for the low-frequency noise phenomena such as random telegraph signal (RTS) and 1/f noise. Random activity of trapping and de-trapping of mobile charge carriers, in to these defects, can be reduced by switching the device ON and OFF periodically. The analysis of the low-frequency noise considers the non-stationary behavior of traps in time-periodic biasing conditions. In this paper, analysis of the low-frequency noise by deriving a model for RTS noise power spectral density for variable duty cycle switched biasing, is presented. It is concluded that the low-frequency noise can be reduced by using a multi-stage configuration of multiple transistors in place of a single transistor. In this configuration, each transistor has a decreased duty cycle and it is shown from simulation that the noise reduction obtained can be as large as 26 dB for a 40 stage configuration.

In this paper, a nine-transistor (9T) Static Random Access Memory (SRAM) bitcell for the low voltage and energy constraint applications is proposed. It is well known that in sub-threshold regime, reliability and process variations are the main design challenges, and standard six-transistor (6T) SRAM bitcell fails to operate in sub-VTH. The proposed design has better read stability and improved process variation tolerant as compared to standard 6T SRAM at low voltage. Simulation results based on 32nm technology node shows that there is 37% improvement in the read stability as compared to standard 6T SRAM bitcell. The proposed design also address the conflicting read and write requirements, therefore, one can optimize the read static noise margin (SNM), write noise margin and write speed for a particular application by selecting the bitcell ratios for read and write operations.

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