Process variation tolerant 9T SRAM bitcell design

Reddy, G. Karthik; Jainwal, Kapil; Singh, Jawar; Mohanty, Saraju P.

doi:10.1109/isqed.2012.6187539

Cited by 13 publications

(4 citation statements)

References 12 publications

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“…In this work, all the designs were carried out for short gate length of 16 nm for MOSFET, 16 nm for FinFET, and 15 nm for GNRFET. Besides, the power consumption of the previous works has not been reported [19,20]. As per the performance analysis in the retention mode, both 6T and 8T SRAM cells do not have significant discrepancy.…”

Section: Snm Extractionmentioning

confidence: 96%

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Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

Natarajamoorthy

Subbiah²,

Alias

et al. 2020

Journal of Nanotechnology

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The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

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Section: Snm Extractionmentioning

confidence: 96%

“…e delay is usually calculated at the point of input-output switching. Power and delay has been calculated using synopsys HSPICE and COSMOSCOPE, respectively, by analyzing transient analysis [19]. Similarly, SNM is calculated using COSMOSCOPE in DC analysis.…”

Section: Snm Extractionmentioning

confidence: 99%

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

Natarajamoorthy

Subbiah²,

Alias

et al. 2020

Journal of Nanotechnology

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“…It is used for inline testers and provides information about the current and voltage in a single plot [19]. In the simulation setup, an independent DC voltage was connected between the QB and ground pins.…”

Section: N-curve Metricmentioning

confidence: 99%

A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

Khan¹,

Perdriau²,

Ramdani³

et al. 2022

IEEE Lett. on Electromagn. Compat. Pract. and Appl.

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This paper evaluates the performance of 6T & 9T static random access memory (SRAM) cells, for data stability and power metrics, with the aim to compare silicon-on-insulator (SOI) and bulk CMOS technologies. Each SRAM topology was designed & simulated in 180 nm 5 V XFAB-SOI and AMS-bulk processes, using optimized parameters and compatible devices. The fundamental variables analyzed were read noise margins, write trip current & voltage as well as leakage current (LC) and static power dissipation (SPD) under process and temperature (PT) variations. The static noise margin (SNM) butterfly curve and N-curve methodologies were used to assess the mentioned parameters. Compared to bulk technology, the SRAM cells designed with SOI were found to have lower SPD & LC, higher data stability, lower write ability, larger sensitivity to process variations and higher resilience to temperature deviations.

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“…[8] modeled the variability using threshold voltage as a source of variability to evaluate stability of 9T SRAMs for the 32nm node. [9] performed a full PVT analysis of 6T SRAM cells down to the 7nm node, however their variability modeling only considered two sources of mismatch: EOT and TOXE, which is inaccurate as the technology shrinks.…”

Section: Introductionmentioning

confidence: 99%

Four-injector variability modeling of FinFET predictive technology models

Royer

López‐Vallejo

Redondo

et al. 2014

2014 5th European Workshop on CMOS Variability (VARI)

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Abstract-The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. In this work we apply the four-injector approach for variability modeling to the simulation of SRAMs with predictive technology models from 20nm down to 7nm nodes. We show that the SRAMs, designed following ITRS roadmap, present stability metrics higher by at least 20% compared to a classical variability modeling approach. Speed estimation is also pessimistic, whereas leakage is underestimated if sub-threshold slope and DIBL mismatch and their correlations with threshold voltage are not considered.

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Process variation tolerant 9T SRAM bitcell design

Cited by 13 publications

References 12 publications

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

Four-injector variability modeling of FinFET predictive technology models

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