Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

Abstract

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

Design and Simulation of Bi-Layer Optimized High K- Dielectric Medium for N-Mosfet with Wild Horse Optimization to Improve Electrical Characteristics

“…The evolution of memory density has to endure to follow the trends in the scaling of logic since memory will continue to make up a significant portion of many future architectures. 9 Higher transistor leakage and factor changes for scalability of traditional six-transistor (6 T) SRAM cells present difficulties. The variation in transistor threshold voltage (Vt), and consequently on-and off-currents, increases as MOSFETs are scaled down to the nanoscale zone due to oxide thickness variations, stochastic dopant fluctuations and line-edge roughness.…”