10T FinFET based SRAM cell with improved stability for low power applications

Sharma, Deepika; Birla, Shilpi

doi:10.1080/00207217.2021.2001868

Cited by 8 publications

(5 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The metrics is analyzed. SRAM cell related with read/write assist technique using SG FinFETs based LECTOR Technique technology is compared with existing designs, like Comparative Study of CMOS and FinFET‐Based SRAM Cell Utilizing SVL (FinFETs‐SRAM‐SVL), 21 SRAM design leveraging material properties of exploratory transistors (FinFETs‐SRAM‐STDCSVL), 22 Leakage lessening in 18 nm FinFET basis 7T SRAM Cell utilizing self‐controllable voltage level strategy (FinFET‐SRAM‐INDEP), 23 Energy efficient SRAM utilizing FinFETs with potential alteration topology (FinFETs‐SRAM‐PAT), 24 Design and Development of Efficient SRAM Cell depending on FinFET for Low Power Memory Applications (FinFETs‐SRAM‐LPMA) 30 and broad analysis of various SRAM cell topologies in 7‐nm FinFET (FinFETs‐SRAM‐RSNM) 31 . Table 1 display parameters values for LECTOR based SG FinFETs.…”

Section: Resultsmentioning

confidence: 99%

“…Sharma and Birla, 24 suggested a 10T FinFET base SRAM cell along stability enhancement for lesser power applications. The suggested method uses two 10 transistor FinFET design static random‐access memory cells.…”

Section: Literature Surveymentioning

confidence: 99%

“…Several techniques have presented in the literature related to SRAM cell for leakage power reduction. But the existing methods have several issues, like leakage current, read with write LPD, propagation delay, and degrade static noise margins 21–27 . These drawbacks have motivated to do this work.…”

Section: Introductionmentioning

confidence: 99%

“…But the existing methods have several issues, like leakage current, read with write LPD, propagation delay, and degrade static noise margins. [21][22][23][24][25][26][27] These drawbacks have motivated to do this work.…”

mentioning

confidence: 99%

See 3 more Smart Citations

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

View full text Add to dashboard Cite

Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

View full text Add to dashboard Cite

show abstract

“…This is also illustrated with the help of conceptual RBL in figure 5(a). Various other SRAM cells that use a separate read buffer, such as 7 T [21], 8 T [22,23], 9 T [11][12][13]23], 10 T [10,14,25] have been reported to deal with the issue encountered in CONV8T. The 10 T SRAM cell proposed in [17] that uses a 4 T read buffer (RB-B), shown in figure 2(b), helps in reducing the RBL leakage current.…”

Section: Existing Read Decoupled Cellsmentioning

confidence: 99%

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Sharif¹,

Ahmad²,

Alam³

2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

Read decoupled SRAM cells were proposed to address the conflicting Read and Write requirements in conventional 6T SRAM cells. However, even read decoupled SRAM cells face several challenges like degraded cell stability, data dependent read bitline (RBL) leakage, deteriorated RBL swing which causes the failure in read sensing at scaled voltages. Therefore, in this work, we propose a read decoupled 9T SRAM cell which improves the read performance. The proposed cell utilizes decoupled read port that significantly improves the read delay, ION/IOFF ratio, bitline leakage as compared to the existing read decoupled cells. The proposed read buffer, having only one transistor in the read path, offers much lower read delay as compared to the existing read buffers. The RBL leakage in the proposed design is also data independent, which significantly improves the RBL sensing margin. We analyse and compare the proposed SRAM cell with existing cells using HSPICE simulations with 16nm FinFET PTM technology. We observe that at a voltage of VDD = 0.35V, the proposed SRAM cell offers ~55% smaller read delay with only 8% increase in leakage power as compared to conventional 6T cell. However, the proposed SRAM cell incurs smallest leakage penalty and offers fastest read operation than the existing read buffer based SRAM cells. Attributed to the negligible bitline leakage in the proposed cell, it offers the highest RBL sensing voltage attributed to closeness of RBL voltage for read ‘1’ to VDD as compared with the other cells. Monte Carlo simulations are also carried out to confirm the robustness of the proposed design under PVT variations. We observe that the proposed SRAM cell is robust and supports voltage scaling and hence could be an attractive choice for low voltage and low power applications.

show abstract

Design and Analysis of Heterojunction Inverted-T P-FinFET on 14nm Technology Node for Use in Low-Power Digital Circuits

Verma

Tripathi

2023

Silicon

View full text Add to dashboard Cite

10T FinFET based SRAM cell with improved stability for low power applications

Cited by 8 publications

References 24 publications

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Design and Analysis of Heterojunction Inverted-T P-FinFET on 14nm Technology Node for Use in Low-Power Digital Circuits

Contact Info

Product

Resources

About