Read decoupled SRAM cells were proposed to address the conflicting Read and Write requirements in conventional 6T SRAM cells. However, even read decoupled SRAM cells face several challenges like degraded cell stability, data dependent read bitline (RBL) leakage, deteriorated RBL swing which causes the failure in read sensing at scaled voltages. Therefore, in this work, we propose a read decoupled 9T SRAM cell which improves the read performance. The proposed cell utilizes decoupled read port that significantly improves the read delay, ION/IOFF ratio, bitline leakage as compared to the existing read decoupled cells. The proposed read buffer, having only one transistor in the read path, offers much lower read delay as compared to the existing read buffers. The RBL leakage in the proposed design is also data independent, which significantly improves the RBL sensing margin. We analyse and compare the proposed SRAM cell with existing cells using HSPICE simulations with 16nm FinFET PTM technology. We observe that at a voltage of VDD = 0.35V, the proposed SRAM cell offers ~55% smaller read delay with only 8% increase in leakage power as compared to conventional 6T cell. However, the proposed SRAM cell incurs smallest leakage penalty and offers fastest read operation than the existing read buffer based SRAM cells. Attributed to the negligible bitline leakage in the proposed cell, it offers the highest RBL sensing voltage attributed to closeness of RBL voltage for read ‘1’ to VDD as compared with the other cells. Monte Carlo simulations are also carried out to confirm the robustness of the proposed design under PVT variations. We observe that the proposed SRAM cell is robust and supports voltage scaling and hence could be an attractive choice for low voltage and low power applications.

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