A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Sharif, Adeeba; Ahmad, Sayeed; Alam, Naushad

doi:10.1088/1361-6641/ac5b19

Cited by 4 publications

(4 citation statements)

References 31 publications

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“…39 By reducing the number of possible half select paths, the half selected cell issue can be reduced. 40 We have single access transistor in the proposed CNTFET based robust and power efficient 8T SRAM, and so node storing "1" will only have voltage difference from respective bit lines and the remaining cells with data "0" will maintain same voltage as bit line. So this reduces half selected issue for SRAM cells by 50%.…”

Section: Cntfetmentioning

confidence: 99%

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

Yalla¹,

Nanda²

2023

ECS J. Solid State Sci. Technol.

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A new carbon nano-tube field-effect transistor (CNTFETs) based power efficient and robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only a single pull-up transistor with high Vt in storage latch. The half-select issue is eliminated because the proposed work uses a de-coupled read port. This CNTFET-based proposed PER-8T cell is analysed for performance parameters of power, delay, and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at a supply voltage of 0.9 V considering the Stanford virtual source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. The effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness, and carbon nano tube diameter values on hold power are analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25°C.

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Section: Cntfetmentioning

confidence: 99%

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

Yalla¹,

Nanda²

2023

ECS J. Solid State Sci. Technol.

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“…The Electrical Quality Metric (EQM) has been utilized for evaluating the overall performance of SRAM cells [46]. The EQM is calculated by using the following formula where: The Electrical Quality Metric (EQM) has been utilized for evaluating the overall performance of SRAM cells [46].…”

Section: E 2 Vr11t Sram Electrical Quality Metric (Eqm)mentioning

confidence: 99%

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Thirugnanam¹,

Soong

Prabhu

et al. 2023

Sensors

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The need for power-efficient devices, such as smart sensor nodes, mobile devices, and portable digital gadgets, is markedly increasing and these devices are becoming commonly used in daily life. These devices continue to demand an energy-efficient cache memory designed on Static Random-Access Memory (SRAM) with enhanced speed, performance, and stability to perform on-chip data processing and faster computations. This paper presents an energy-efficient and variability-resilient 11T (E2VR11T) SRAM cell, which is designed with a novel Data-Aware Read–Write Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended read and dynamic differential write circuits. The simulated results in a 45 nm CMOS technology exhibit 71.63% and 58.77% lower read energy than ST9T and LP10T and lower write energies of 28.25% and 51.79% against S8T and LP10T cells, respectively. The leakage power is reduced by 56.32% and 40.90% compared to ST9T and LP10T cells. The read static noise margin (RSNM) is improved by 1.94× and 0.18×, while the write noise margin (WNM) is improved by 19.57% and 8.70% against C6T and S8T cells. The variability investigation using the Monte Carlo simulation on 5000 samples highly validates the robustness and variability resilience of the proposed cell. The improved overall performance of the proposed E2VR11T cell makes it suitable for low-power applications.

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“…A low leakage junctionless MOSFET-based 6T SRAM cell is presented in [15]. The FinFET-based low leakage 6T and 8T SRAM cells are also studied in [16][17][18]. A 6T SRAM cell using negative capacitance JL FinFET is presented in [19] which consumes less power than conventional 6T SRAM.…”

Section: Introductionmentioning

confidence: 99%

“…A 6T SRAM cell using negative capacitance JL FinFET is presented in [19] which consumes less power than conventional 6T SRAM. The literature mostly focused on 6T SRAM cell using inversion mode and junctionless FinFET [16][17][18][19][20][21]. This manuscript presents an 8T-SRAM cell using junctionless tri-gate FinFET with stack-channel and compares it with the conventional 8T-SRAM cell in terms of static noise margin, leakage power, and delay.…”

Section: Introductionmentioning

confidence: 99%

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Singh,

Chaudhary,

Dewan

et al. 2024

Eng. Res. Express

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Junctionless FinFET devices are a substitute for conventional FinFET devices due to their less short channel effects and easy manufacturing at sub 22-nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si0.75Ge0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack eﬀect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, -1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

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A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Cited by 4 publications

References 31 publications

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read–Write Assist (DARWA) Technique for Low-Power Applications

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

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