Analysis of a Controller-Based All-Digital Phase-Locked Loop

Abstract

A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly-phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed-loop system of the proposed ADPLL eliminates phase error. Time-domain response of the behavioral-level simulation of the proposed structure on 130-nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.

A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

“…The circuit is intended for medical implantable transceivers operating in the MICS band and is based on a programmable integer-N PLL. In our previous studies [5], [6], we confirmed the system stability and functionality of controller-based ADPLL through phase-domain modeling. In this paper, we focus on circuit design and implementa-Copyright c 2016 The Institute of Electronics, Information and Communication Engineers tion details as well as measurement results in the MICS frequency band for medical applications.…”

“…From similar behavior-level simulation results for N=27-2700 and M PI =2 4 , 2 5 , and 2 6 and their comparison with the s-domain analytical model, the empirical approximations for α f , ρ, and α p were obtained in this study as…”

“…The controller has two types of digital control words based on the counter operation, and its two transfer functions K cnt,dco and K cnt,ps for the DCO and PS in discrete-time z-domain are respectively given by [5], [6]…”

“…The ADPLL has been mathematically analyzed as z-domain and linearly approximated s-domain models in [5], [6], [8]. It is common to approximate the z-transform as a linear continuous-time system in the s-domain.…”

“…3 (a), as M PI increases, the phase domain model simulation of the ADPLL shows that the loop bandwidth increases. The sdomain model has been validated against Verilog-HDL simulations in the previous studies [5], [6]. From the behaviorlevel simulation shown in Fig.…”